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These are the Lecture Slides of Functional Verification which includes Reusable Verification Components, Verilog Implementation, Implementation, Autonomous Generation and Monitoring, Input and Output Paths, Verifying Configurable Designs, Reusable Test Harness, Testcase Specific Code, Abstraction etc. Key important points are: Introduction, Verification Using Rulebase, Brief Review, Genbuff, Modeling the Environment, Formulating Rules, Running Rulebase, Timing Diagrams, Partition Selection, Com
Typology: Slides
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design (HDL)
environ. (EDL)
spec (sugar)
RuleBase
pass / fail
GenBuf Example
GenBuf is a design block that queues words of data (32 bits) sent by four senders. GenBuf then transmits the data to two receivers. The four senders are equivalent and the two receivers are equivalent.
STOB_REQ(0) BTOS_ACK(0) Sender0 DI_0_(0..31)
Sender
Sender
Sender
G E N B U F
STOB_REQ(1) BTOS_ACK(1) DI_1_(0..31) STOB_REQ(2) BTOS_ACK(2) DI_2_(0..31) STOB_REQ(3) BTOS_ACK(3) DI_3_(0..31)
BTOR_REQ(0) RTOB_ACK(0)
BTOR_REQ(1) RTOB_ACK(1)
Receiver
Receiver
D0(0..31)
Communication w/ Receivers takes place by means of a 4-phase handshaking When GenBuf has data, it will choose a receiver (y=0 or 1) and will initiate a data transfer by asserting BTOR_REQ(y) ("Buffer to Receiver Requests y") When the receiver is ready, it will assert RTOB_ACK(y) ("Receiver to Buffer Acknowledge") One cycle after RTOB_ACK(y) is asserted, GenBuf will put the data on the data bus (DO(0..31)) The receiver will indicate to GenBuf that it has read the data by deasserting RTOB_ACK(y) GenBuf should wait for RTOB_ACK(y) to be deasserted before it starts a new transaction GenBuf uses a fair scheme to select the Receiver
Sender to GenBuf Signal Name (^) Description
STOB_REQ(0) Request Input for senders 0-
DI_0_(0..31) Data in for Sender
DI_1_(0..31) Data In for Sender
DI_2_(0..31) Data In for Sender
DI_3_(0..31) Data In for Sender
GenBuf to Sender Signal Name Description
BTOS_ACK(0..3) Acknowledgment for Senders 0-
Other inputs to GenBuf Signal Name (^) Description
RST Reset Signal: Active High (set to 1 for 2 cycles then to 0)
CLK Clock (set to 1)
ERROR_FOUND(1..6) Set to 0
Path quantifiers A - for all paths E - there exists a path Tense Operators X p - p holds at the next cycle F p - p holds sometime in the future G p - p holds globally from the present time p U q - p holds until q holds
Sugar - Bounded-Range Operators
{e0,e1,e2,...}(f) f must hold on the last cycle of all computations that agree with the sequence e0 at cycle 0, e1 at cycle 1, e2 at cycle 2, etc.
Example: ”every req on cycle X that gets a gnt at cycle X+1 and doesn't get retried at cycle X+2, should cause busy to be active at cycle X+2" AG {[*],req,gnt,!retry}(busy)
r must occur eventually
Weak version: does not require r eventually occur Sugar q until! r Strong version - equivalent to AU