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- (^) Peripheral Devices
- (^) Input-Output Interface
- Asynchronous Data Transfer
- (^) Modes of Transfer
- (^) Priority Interrupt
- Direct Memory Access
- (^) Input-Output Processor
- (^) Serial Communication
INPUT-OUTPUT ORGANIZATION
PERIPHERAL DEVICES
Input Devices
- (^) Keyboard
- (^) Optical input devices
- Card Reader
- Paper Tape Reader
- Bar code reader
- Digitizer
- Optical Mark Reader
- (^) Magnetic Input Devices
- (^) Screen Input Devices
- Touch Screen
- Light Pen
- Mouse
- (^) Analog Input Devices
Output Devices
- (^) Card Puncher, Paper Tape Puncher
- (^) CRT
- (^) Printer (Impact, Ink Jet, Laser, Dot Matrix)
- (^) Plotter
- (^) Analog
- (^) Voice Peripheral Devices
I/O BUS AND INTERFACE MODULES
Each peripheral has an interface module associated with it Interface
- Decodes the device address (device code)
- Decodes the commands (operation)
- Provides signals for the peripheral controller
- Synchronizes the data flow and supervises the transfer rate between peripheral and CPU or Memory Typical I/O instruction (Command) Op. code (^) Device address Function code Input/Output Interfaces Processor Interface Keyboard and display terminal Magnetic tape Printer Interface Interface Interface Data Address Control Magnetic disk I/O bus
CONNECTION OF I/O BUS
Connection of I/O Bus to One Interface Connection of I/O Bus to CPU Input/Output Interfaces I/O bus Op. code Device address Function code Accumulator register Computer I/O control Sense lines Data lines Function code lines Device address lines
CPU
I/O
bus Device address Command decoder Function code Data lines Buffer register Peripheral register Status register Sense lines Output peripheral device and controller AD = 1101 (^) Interface Logic
ISOLATED vs MEMORY MAPPED I/O
- Separate I/O read/write control lines in addition to memory read/write control lines
- Separate (isolated) memory and I/O address spaces
- Distinct input and output instructions Isolated I/O Memory-mapped I/O
- A single set of read/write control lines (no distinction between memory and I/O transfer)
- Memory and I/O addresses share the common address space -> reduces memory address range available
- No specific input or output instruction -> The same memory reference instructions can be used for I/O transfers
- Considerable flexibility in handling I/O operations Input/Output Interfaces
I/O INTERFACE
- Information in each port can be assigned a meaning depending on the mode of operation of the I/O device -> Port A = Data; Port B = Command; Port C = Status
- CPU initializes(loads) each port by transferring a byte to the Control Register -> Allows CPU can define the mode of operation of each port -> Programmable Port : By changing the bits in the control register, it is possible to change the interface characteristics CS RS1 RS0 Register selected 0 x x None - data bus in high-impedence 1 0 0 Port A register 1 0 1 Port B register 1 1 0 Control register 1 1 1 Status register Programmable Interface Input/Output Interfaces Chip select Register select Register select I/O read I/O write CS RS RS RD WR Timing and Control Bus buffers Bidirectional data bus Port A register Port B register Control register Status register I/O data I/O data Control Status Internal bus
CPU
I/O
Device
- Employs a single control line to time each transfer
- The strobe may be activated by either the source or the destination unit
STROBE CONTROL
Source unit Destination unit Data bus Strobe Data Strobe Valid data Block Diagram Timing Diagram Source-Initiated Strobe for Data Transfer Source unit Destination unit Data bus Strobe Data Strobe Valid data Block Diagram Asynchronous Data Transfer Destination-Initiated Strobe for Data Transfer Timing Diagram
HANDSHAKING
Strobe Methods Source-Initiated The source unit that initiates the transfer has no way of knowing whether the destination unit has actually received data Destination-Initiated The destination unit that initiates the transfer no way of knowing whether the source has actually placed the data on the bus To solve this problem, the HANDSHAKE method introduces a second control signal to provide a Reply to the unit that initiates the transfer Asynchronous Data Transfer
DESTINATION-INITIATED TRANSFER USING HANDSHAKE
- Handshaking provides a high degree of flexibility and reliability because the successful completion of a data transfer relies on active participation by both units
- If one unit is faulty, data transfer will not be completed -> Can be detected by means of a timeout mechanism Block Diagram Timing Diagram Source unit Destination unit Data bus Ready for data Data valid Sequence of Events Place data on bus. Enable data valid. Source unit Destination unit Ready to accept data. Enable ready for data. Disable data valid. Invalidate data on bus (initial state). Accept data from bus. Disable ready for data. Ready for data Data valid Data bus Valid data Asynchronous Data Transfer
ASYNCHRONOUS SERIAL TRANSFER
Asynchronous serial transfer Synchronous serial transfer Asynchronous parallel transfer Synchronous parallel transfer
- Employs special bits which are inserted at both ends of the character code
- Each character consists of three parts; Start bit; Data bits; Stop bits. A character can be detected by the receiver from the knowledge of 4 rules;
- When data are not being sent, the line is kept in the 1-state (idle state)
- The initiation of a character transmission is detected by a Start Bit , which is always a 0
- The character bits always follow the Start Bit
- After the last character , a Stop Bit is detected when the line returns to the 1-state for at least 1 bit time The receiver knows in advance the transfer rate of the bits and the number of information bits to expect Four Different Types of Transfer Asynchronous Serial Transfer Start bit (1 bit) Stop bits Character bits 1 1 0 0 0 1 0 1 (at least 1 bit) Asynchronous Data Transfer
