IMSE 643 INDUSTRIAL SIMULATION
HOMEWORK PROJECT #1
(Due by 5:00PM Friday, September 24)
Page 1
A computer memory packaging facility consists of six workstations: one
inspection/testing station, one die separation station, two Integrated Circuit packaging stations, a
backup packaging station, and a shipping station. Wafers of two different sizes of 8-inch (for
1GB DDR RAMs) and 12-inch (for 2BG DDR RAMs) supplied by two upstream wafer
manufacturers are tested, cutted, and packaged using the same facility.
The first upstream wafer factory sends parts for 8” wafers to the subsystem 10 sets at a
time and the inter-arrival times are exponentially distributed with a mean of 12 hours. The
second upstream wafer factory sends 12” wafers to the subsystem 20 sets at a time, and the
inter-arrival time follows a normal distribution with the mean of 36 hours and the standard
deviation of 6 hours. The wafers for both sizes are tested upon arrival at the inspection/testing
station. The inspection station tests the parts for any damage during manufacturing and shipping.
If the wafer are confirmed good, it is sent to the die separation station, otherwise the wafer for
the model is discarded. The Die Separation Station separates an 8” wafer to 4 dies (of 1GB DDR
RAM chips), and an 12” wafer to 8 dies (of 2GB DDR RAM chips). The processing times of the
separation and inspection stations follow triangular distributions and the corresponding
parameters are given in Tables 2 and 3. The separated dies are then forwarded to the packaging
stations for wire bonding and plastic packaging operations.
The die packaging process consists of two packaging workstations that put the die into an
plastic package, bond the golden wires to the die and sealed with packaging material. Dies for
2GB DDR must go to the packaging station 1, and then to the packaging station 2. Dies for 1GB
DDR must go to the packaging station 2 and then to the packaging station 1. Packaging station 2
has only 128 buffer spaces. If the packaging station 2 runs out of buffer spaces, the parts are re-
routed to another backup station. The processing time for the backup station is the same both
memory chips and is distributed uniformly between 0.5 to 15 minutes.
After the chips have been packaged, they are sent to the inspection/testing station. Then,
the inspection station tests the functionalities of the packaged memory chips. If a chip is
confirmed as a good product, the chip will be sent to the shipping department and then the chip
departs the system. If the memory chip is considered as a non-confirmed product, it will be
discarded. If the memory chips goes through the backup assembly station, it is considered to be
inspected on-line and does not need to be re-inspected at the inspection station. It would directly
go to the shipping station.
The processing times for the two packaging stations, separation station and the incoming
inspection station follow triangular distributions. The processing times for the shipping station,
and the post-packaging inspection is based on normal distribution. The corresponding parameters
are given below:
Table 1. Processing Times for the Packaging Stations (in minutes)
Packaging 1 Packaging 2
Min. Mode Max. Min. Mode Max.
2GB 1.0 2.0 3.0 1.0 2.5 4.0
1GB 1.0 1.5 4.0 0.5 2.0 3.0
