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Homework 5 for ENEE 244 Spring 2006: Digital Logic Circuits - Prof. Rajeev Kumar Barua, Assignments of Electrical and Electronics Engineering

The homework assignment for enee 244 spring 2006, focusing on digital logic circuits. Students are required to fill up truth tables, design latches, tabulate and derive equations for flip-flops, and explain the function of sequential circuits. No external inputs or outputs are provided in some problems.

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Pre 2010

Uploaded on 02/13/2009

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ENEE 244 (01**). Spring 2006
Homework 5
Due back in class on Friday, April 28.
1. Fill up the function table (truth table) for the following latch. How is this latch related to those
described in the lectures and in the textbook? (Describe similarities and differences with the
most closely related latch).
2. The gated SR latch has unpredictable behavior if the S and R inputs are both equal to 1 when C
is 1. One way to solve this problem is to create a setdominated gated SR latch in which the
condition S=R=1 causes the latch to be set to 1. Design a setdominated gated SR latch. Show
the circuit. (Hint: Let the original circuit remain as it is, but add some external circuitry.)
3. A PN flip-flop has 4 operations: clear to 0, no change, complement, and set to 1, when inputs P
and N are 00,01,10, and 11, respectively. Tabulate its characteristic table (called the simplified
function table by the Givone text). Derive its characteristic equation.
4. Show how to implement a D flipflop starting with a JK flipflop.
5. A sequential circuit contains two flip-flops T1 and T2. The circuit has no external inputs. The
only external output are the values of the current state (Q1 and Q2). The flip-flop inputs are
connected as:
T1 = Q1 + Q2
T2 = Q1’ + Q2
Explain the intuitive function that the circuit performs.
6. A sequential circuit has two JK flipflops with outputs Q1 and Q2 and one input x. The circuit
is described by the following flipflop input equations:
J1 = x
J2= x
K1= Q2’
K2= Q1
a) Derive the next-state equations for the circuit.
b) Draw the state diagram.
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ENEE 244 (01**). Spring 2006

Homework 5

Due back in class on Friday, April 28.

  1. Fill up the function table (truth table) for the following latch. How is this latch related to those described in the lectures and in the textbook? (Describe similarities and differences with the most closely related latch).
  2. The gated SR latch has unpredictable behavior if the S and R inputs are both equal to 1 when C is 1. One way to solve this problem is to create a set−dominated gated SR latch in which the condition S=R=1 causes the latch to be set to 1. Design a set−dominated gated SR latch. Show the circuit. ( Hint : Let the original circuit remain as it is, but add some external circuitry.)
  3. A PN flip-flop has 4 operations: clear to 0, no change, complement, and set to 1, when inputs P and N are 00,01,10, and 11, respectively. Tabulate its characteristic table (called the simplified function table by the Givone text). Derive its characteristic equation.
  4. Show how to implement a D flip−flop starting with a JK flip−flop.
  5. A sequential circuit contains two flip-flops T1 and T2. The circuit has no external inputs. The only external output are the values of the current state (Q1 and Q2). The flip-flop inputs are connected as: T1 = Q1 + Q T2 = Q1’ + Q Explain the intuitive function that the circuit performs.
  6. A sequential circuit has two JK flip−flops with outputs Q1 and Q2 and one input x. The circuit is described by the following flip−flop input equations: J1 = x J2= x K1= Q2’ K2= Q a) Derive the next-state equations for the circuit. b) Draw the state diagram.

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  1. Derive the state table for the circuit drawn below.
  2. Draw the state diagram for a Mealy machine that accepts an infinite sequence of bits, and outputs a 1 if the last four bits input are 1100; otherwise the output is 0. For example, for the input below, the output should be as shown: INPUT: 00110110011..... OUTPUT:00000000100.... Use no more than 4 states in your state diagram. Be careful that your solution works for the above input. What is the minimum number of flip flops needed for implementing your state diagram?
  3. Derive the state diagram for a Moore machine that has an input w and an output z. The machine has to generate z=1 when the pervious four values of w were 1001 or 1111; otherwise the output z=0. Overlapping input patterns are allowed. Example: w: 010111100110011111.... z: 000000100100010011... Use no more than eight states in your solution. What is the minimum number of flip flops needed for implementing your state diagram?