EE 1210 Homework 4 Name:____________________________
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Homework 4 - Schematic Diagrams - Introduction to Logic System Design | EE 1210, Assignments of Electrical and Electronics Engineering
Material Type: Assignment; Professor: Bolding; Class: Introduction to Logic System Design; Subject: Electrical Engineering; University: Seattle Pacific University; Term: Unknown 1989;
Typology: Assignments
Pre 2010
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EE 1210 Homework 4 Name:____________________________ 39a. 39b. 39c.
F
AB
C
B
C
A
F
AB
C
B
C
A
Q
DE
F
E
F
D
41a. 41b. 41c.
F
AB
C
B
C
A
F
AB
C
B
C
A
A
C
D
F
AB
CD
B
m 0 m 1 m 4 m 5 m 12 m 13 m 8 m 9 m 3 m 2 m 7 m 6 m 15 m 14 m 11 m 10
46b. 46c. 47a.
F
XY
Z
Y
Z
X
F
AB
C
B
C
A
A
C
D
F
AB
CD
B
m 0 m 1 m 4 m 5 m 12 m 13 m 8 m 9 m 3 m 2 m 7 m 6 m 15 m 14 m 11 m 10
47b.
W
Y
Z
F
WX
YZ
X
m 0 m 1 m 4 m 5 m 12 m 13 m 8 m 9 m 3 m 2 m 7 m 6 m 15 m 14 m 11 m 10