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ENEE 244 (01**). Spring 2006
Homework 4
Due back in class on Friday, April 7.
- Implement the following Boolean expression with exclusive-OR and AND gates only: F = AB'CD' + A'BCD' + AB'C'D + A'BC'D.
F = AB’CD’ + A’BCD’ + AB’C’D + A’BC’D = AB’(CD’ + C’D) + A’B( CD’ + C’D) = (AB’ + A’B) ( CD’ + C’D) = ( A ⊕ B) ( C ⊕ D)
- Determine whether the gate set {AND, EXCLUSIVE-OR} is functionally complete. Prove your answer.
We know that {AND, OR, NOT} is functionally complete.
To prove that another set is functionally complete, it is enough to show that AND, OR and NOT can each be implemented in terms of the new set.
Here that implies that OR and NOT need to be implemented using AND, XOR.
To implement NOT: a’ = a’.1 + a.0 = a ⊕ 1
To implement OR: A + b = (a + b)’’ = (a’.b’)’ //Using Demorgan’s law. This last term contains only AND and NOT gates, each of which have already been shown to be expressible in the set {AND, XOR}.
Hence both NOT and OR can be implemented in terms of {AND,XOR}. ⇒ {AND,XOR} is functionally complete.
- A two-level all-NAND implementation of a complex logic function z (x1,x2,......xn) has been fabricated in a IC at considerable expense. As the IC is about to be installed in a system it is discovered that all the gates it contains are actually NORs instead of NANDs. It is now too late to fix the IC itself, but it is possible to add some extra logic to the IC"s input/output lines. So what should the IC designer do to fix this flaw so that the IC in question can be used?
We need:
But we have:
We can add NOT gates at all inputs and the output to convert the second into the first: This is because, at inputs:
This is a NAND gate with an extra NOT gate at output. We can move this extra NOT gate between the two levels of the circuit to the inputs of the second level. This gives:
Since a NOT gate is added at the output as well, this second-level gate becomes a NAND gate as well. Thus, adding NOT gates at all inputs and the output is equivalent to converting all the internal NOR gates to NAND gates, as desired.
- Demonstrate how to implement a 6:64 decoder using generic 2:4 and 4:16 decoders. The input decoders have enable inputs.
To design a 6:64 decoder let the inputs be a,b,c,d,e,f and let the outputs be D0−D63. The design is as shown below. E: enable input o/p: output
- A majority function F takes three 1-bit inputs a,b and c, and produces a single bit as output that is one if and only if two or more bits of the input are one. Design this circuit using an 8:1 multiplexor.
We can write F directly by observing the minterms whose numerical values have two or more bits which are 1. F = Σ m (011,101,110,111) = Σ m (3,5,6,7) To implement a function using a MUX, we provide the function inputs as the select inputs to the MUX, and connect the minterms in the canonical form to 1. Thus the circuit is:
- The outputs of a 3-to-8 decoder are connected in order to the inputs of an 8-to-1 MUX. The inputs of the decoder are a,b and c; the select inputs of the MUX are d,e and f. What function does the 1-bit output of the MUX implement in terms of a,b,c,d,e and f?
A decoder turns its i th^ output high if the input abc=i. A MUX transmits the value of its j th^ data input to the output if the select input def=j.
Thus a 1 will be transmitted to the output by the MUX only if i=j; and 0 otherwise. Hence the output function F is 1 if the number abc = def. More formally:
F = (a☉d).(b☉e).(c☉f) // ☉ is XNOR.
8 to 1 MUX
0
1
0 0
0
1
1 1
F
a b c
