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Hi frequency SPICE Parameters for use with simulations
Typology: Lecture notes
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26.2 MHz
variation
1/100 decade
1/28 decade
1/15 decade
25.6 MHz 24.6 MHz 22.5 MHz
two zeros ( ω p 1 ) ( ω p1a)
5 BCMF 4VNNBSZ PG #+5 BNQMJmFS IJHIGSFRVFODZ QPMF MPDBUJPOT
Amplifier Type Pole Locations (rad/s.)
Note: R'c = Rc // r o , R's = Rs + rb , Ri = r // R's, and R'e = Re // r o
Common-emitter
(single pole)
(use the smaller)
s c
r // R' C + (1 + gm R' ) C
or
c
m
g
Common-emitter
(two poles)
1
i c c
m
C g C C
' p1A p1A i c
Common-emitter
with emitter
degeneration
s F e
F s c s e c e s c s e
R' + + 1 + R
1 + R' R + R' R + R R + R' + R C + R' + R C
r
r r
Common-collector
s e
s e s e
r
r C r C
Common-base T^
c
ω ω
ω
ϖ
ϖ
ϖ
ϖ ϖ
ϖ
ϖ
ϖ ϖ
ϖ
ϖ μ
μ μ
μ
μ
μ
μ
μ
'3&26&/$: 3&410/4& 0' 53"/44503 ".1-'&*
5BCMF 4VNNBSZ PG '&5 BNQMJmFS IJHIGSFRVFODZ QPMF MPDBUJPOT
Common-source
(single pole)
(use the smaller)
' ' D G
Cgs 1 gm R Cgd R
or
D
1
R (^) gd g m
Common-source
(two poles)
p1A (^) ' ' ' '
G D G D
1
R 1 R R R gs m gd gd
C g C C
, (^) ' ' p1A
p1A G D
1
R R gs gd
C C
Common-source
with source
degeneration
D S
3 3 G S
R 1 R
1 R R
d m d
m d gd d gs
r g r
g r R R C R R r C
where R 3 (^) R R RG D + R R + R RG S D S
Common-drain
' S
' ' ' ' G S G S
1 R
R R R 1 R
m
gs m gd
g
C g C
Common-gate
S
S
R
Cgs 1 gm R
' D
1
Cgd R
Note: R'G RG rg , R'D rd // R (^) D , and R'S rd // RS
Amplifier Type (^) Pole Locations (rad/s.)
$0/$-6%/( 3&."3,4 *
Source of Parameters
Conversion to SPICE
Parameters
Conversion to Hybrid-
Model Parameters
(1)
Manufacturer’s Data Books
Ciss @ VGS = 0
capacitance
Crss @ VGS = 0
capacitance
rss gd (^) m
iss rss gs (^) m
CGD = Crss
CGS = Ciss - Crss
SPICE Models
CGD – zero-bias gate-drain
capacitance
CGS – zero-bias gate-source
capacitance
GD
C gd (^) m
GS
C gs (^) m
M = m 0. 5
IC Design Models
Cgdo – zero-bias gate-drain
capacitance
Cgso – zero-bias gate-source
capacitance
GD
gdo
gd m
gso gs (^) m
CGD = Cgdo
CGS = Cgso
NOTES: (1) Use quiescent values for VGD and VGS in the equations in this column.
(2)The values for and m are device dependent. Typical values are as = 0.6 and m = 0.5.
SPICE default values are = 1.0 and m = 0.
(3) The subscripted junction voltages are for n -channel JFETs. The equations for p -channel
JFETs are identical with these subscripts reversed.
ψ ψ ψ ψ ψ ψ
ψ ψ
ψ
ψ
'3&26&/$: 3&410/4& 0' 53"/44503 ".1-'&*
Source of Parameters
Conversion to SPICE
Parameters
Conversion to Hybrid-
Model Parameters
(1)
Manufacturer’s Data Books
Ciss @ VGS – input capacitance
Crss @ VGS – reverse transfer
capacitance
Coss @ VGS – output
capacitance
Cgs Ciss – Crss
Cgd Crss
Cds Coss – Crss
OX
iss rss
C rss
SPICE Models
CGDO – zero-bias gate-drain
capacitance
CGSO – zero-bias gate-source
capacitance
VTO – threshold voltage
KP – transconductance
coefficient
Cgd = CGDO W
OX gs
Cds = 0
OX = 3.9^ o
= 3.9(8.51) pF/m
for SiO 2
IC Design Models
Levels 2, 3, and 4
PSpice Models
Levels 2, 3, and 4
PSpice Parameters
Levels 2, 3, and 4
PSpice Parameters
NOTES: (1) Default geometry parameters in PSpice are L = W = 100 μ m. In SPICE2,
the default geometry parameters are L = W = 1m. Setting L = W = 100μm or less in the
MOSFET model statement is recommended. Failure to make L = W affects the constants
used to determine the DC operating point.
(2) The value for (^) OX is dependent on the gate insulation material. The value of 3.9 (^) O is for
SiO 2 insulated gates only.
(3) Integrated circuit parameters require the most accurate representation of the physical
realization of the device. Detailed device geometry information is required. More complex
models of the MOSFET are used in specifying parameters for IC design. These models are
beyond the scope of this text: the simple model presented in this text does not have
sufficient detail to be used for IC designs.
ε
ε ε
ε
ε ε