Docsity
Docsity

Prepare for your exams
Prepare for your exams

Study with the several resources on Docsity


Earn points to download
Earn points to download

Earn points by helping other students or get them with a premium plan


Guidelines and tips
Guidelines and tips

Great Ideas in Computer Architecture MIPS Instruction Formats, Study notes of Architecture

For a detailed description of field usage and instruction type for each instruction, see the. MIPS Green Card. 6/27/2012.

Typology: Study notes

2021/2022

Uploaded on 09/27/2022

anjushri
anjushri 🇺🇸

4.8

(14)

243 documents

1 / 67

Toggle sidebar

This page cannot be seen from the preview

Don't miss anything!

bg1
Instructor: JustinHsia
6/27/2012 Summer2012‐‐ Lecture#7 1
CS61C:GreatIdeasin
ComputerArchitecture
MIPSInstruction
Formats
pf3
pf4
pf5
pf8
pf9
pfa
pfd
pfe
pff
pf12
pf13
pf14
pf15
pf16
pf17
pf18
pf19
pf1a
pf1b
pf1c
pf1d
pf1e
pf1f
pf20
pf21
pf22
pf23
pf24
pf25
pf26
pf27
pf28
pf29
pf2a
pf2b
pf2c
pf2d
pf2e
pf2f
pf30
pf31
pf32
pf33
pf34
pf35
pf36
pf37
pf38
pf39
pf3a
pf3b
pf3c
pf3d
pf3e
pf3f
pf40
pf41
pf42
pf43

Partial preview of the text

Download Great Ideas in Computer Architecture MIPS Instruction Formats and more Study notes Architecture in PDF only on Docsity!

Instructor:^ Justin

Hsia

6/27/^

Summer^2012 ‐‐^ Lecture^ #^

CS^ 61C:^ Great

Ideas^ in

Computer^ Architecture^ MIPS^ InstructionFormats

Review^ of^ Last

Lecture

-^ New^ registers:

$a0-$a3,^ $v0-$v

,^ $ra,^ $sp

-^ Also:^ $at,^ $k0-k

,^ $gp,^ $fp,^ PC

-^ New^ instructions:

slt,^ la,^ li,

jal,^ jr

-^ Saved^ registers:

$s0-$s7,^

$sp,^ $ra

Volatile^ registers:

$t0-$t9,^ $v0-$v

$a0-$a

-^ CalleR saves^ volatile

registers^ it^ is^ using

before making^ a^ procedure

call

-^ CalleE saves^ saved

registers^ it^ intends

to^ use 6/27/^

Summer^2012 ‐‐^ Lecture^ #^

Great^ Idea^ #1:

Levels^ of Representation/Interpretation6/27/2012 Summer

2012 ‐‐^ Lecture^ #^ lw^ $t0,^ 0($2)lw^ $t1,^ 4($2)sw^ $t1,^ 0($2)sw^ $t0,^ 4($2) Higher‐Level^ LanguageProgram^ (e.g.^ C)^ Compiler Assembly^ Language^ Program^ (e.g.^ MIPS) Assembler Machine^ Language^ Program^ (MIPS) Machine Interpretation Hardware^ Architecture^ Description(e.g.^ block^ diagrams)

temp^ =^ v[k];v[k]^ =^ v[k+1];v[k+1]^ =^ temp; 0000 1001 1100 0110 1010 1111 0101

1000 1010 1111 0101 1000 0000 1001 1100

0110 1100 0110 1010 1111 0101 1000 0000

1001 0101 1000 0000 1001 1100 0110 1010

1111 Architecture Implementation^ Logic^ Circuit^ Description(Circuit^ Schematic^ Diagrams)

We__are__here._

Agenda

-^ Stored‐Program

Concept

-^ R‐Format •^ Administrivia •^ I‐Format^ –^ Branching^ and

PC‐Relative^ Addressing

-^ J‐Format •^ Bonus:^ Assembly

Practice

-^ Bonus:^ Disassembly

Practice

6/27/^

Summer^2012 ‐‐^ Lecture^ #^

Binary^ Compatibility • Programs are^ distributed^ in

binary^ form

-^ Programs^ bound^ to

specific^ instruction^ set

-^ i.e.^ different^ versions

for^ (old)^ Macs vs.^ PCs

-^ New^ machines^

want^ to^ run^ old^ programs

(“binaries”) as^ well^ as^ programs

compiled^ to^ new

instructions

-^ Leads^ to^ “backward

compatible”^ instruction

sets^ that evolve^ over^ time^ –^ The^ selection^ of^ Intel

80x86^ in^1981 for^ 1st

IBM^ PC^ is^ major reason^ latest^ PCs^ still

use^ 80x86^ instruction

set^ (Pentium 4);^ you^ could^ still^ run

program^ from^1981 PC^ today 6/27/^

Summer^2012 ‐‐^ Lecture^ #^

Instructions

as^ Numbers

-^ Currently^ all^ data

we^ work^ with^ is

in^ words

(32‐bit^ blocks)^ –^ Each^ register^ is

a^ word^ in^ length – lw and sw both^ access^ one^ word

of^ memory

-^ So^ how^ do^ we

represent^ instructions? – Remember: computer^ only^ understands

1s^ and 0s,^ so^ “add $t0,$0,$

”^ is^ meaningless.

-^ MIPS^ wants^ simplicity:

since^ data^ is^ in^ words,

let instructions^ be^ in

words,^ too 6/27/^

Summer^2012 ‐‐^ Lecture^ #^

Instruction^

Formats

-^ I‐Format: instructions

with^ immediates,

lw/sw^ (offset^ is

immediate),^ and

beq/bne

-^ But^ not^ the^ shift

instructions

-^ J‐Format:^ j^ and

jal

-^ But^ not^ jr • R‐Format: all^ other

instructions

-^ It^ will^ soon^ become

clear^ why^ the^ instructions

have^ been^ partitioned

in^ this^ way

6/27/^

Summer^2012 ‐‐^ Lecture^ #^

Agenda

-^ Stored‐Program

Concept

-^ R‐Format •^ Administrivia •^ I‐Format^ –^ Branching^ and

PC‐Relative^ Addressing

-^ J‐Format •^ Bonus:^ Assembly

Practice

-^ Bonus:^ Disassembly

Practice

6/27/^

Summer^2012 ‐‐^ Lecture^ #^

R‐Format^ Instructions

-^ opcode^ (6):^

partially^ specifies

operation

-^ Set^ at^ 0b000000 for

all^ R‐Format^ instructions

-^ funct^ (6):^ combined

with^ opcode,^ this

number

exactly^ specifies

the^ instruction

-^ How^ many^ R‐format

instructions^ can

we^ encode?

-^ opcode^ is^ fixed,

so^64

-^ Why^ aren’t^ these

a^ single^12 ‐bit^ field?

-^ We’ll^ answer^ this

later 6/27/^

Summer^2012 ‐‐^ Lecture^ #^

R‐Format^ Instructions

-^ rs^ (5):^ specifies

register^ containing

st^1 operand

(“source^ register”) • rt^ (5):^ specifies

register^ containing

nd^2 operand

(“target^ register”

  • name^ is^ misleading) -^ rd^ (5):^ specifies

register^ that^ receives

the^ result

of^ the^ computation

(“destination^ register”)

-^ Recall:^ MIPS^ has

32 registers

-^ Fit^ perfectly^ in^ a^

5 ‐bit^ field^ (use^ register

numbers)

-^ These^ map^ intuitively

to^ instructions

-^ e.g.^ add^ dst,src1,src

^ add^ rd,rs,rt

-^ Depending^ on^ instruction,

field^ may^ not^ be^ used 6/27/^

Summer^2012 ‐‐^ Lecture^ #^

R‐Format^ Example

-^ MIPS^ Instruction:^ add^ $8,$9,$10 •^ Pseudo‐code^ (“OPERATION”

column):

add^ R[rd]^ =

R[rs]^ +^ R[rt]

-^ Fields:^ opcode^ =^0

(look^ up on

Green^ Sheet) funct^ =^32

(look^ up on^ Green^

Sheet) rd^ =^8

(destination) rs^ =^9

(first^ operand ) rt^ =^10

(second^ operand ) shamt^ =^0

(not^ a^ shift) 6/27/^

Summer^2012 ‐‐^ Lecture^ #^

R‐Format^ Example

-^ MIPS^ Instruction:

add^ $8,$9,$

Field^ representation

(binary): hex^ representation:^

0x 012A 4020 decimal^ representation:

19,546, Called^ a^ Machine^ Language

Instruction

two

6/27/^

Summer^2012 ‐‐^ Lecture^ #^

17 0

31

0

000000

0

Agenda

-^ Stored‐Program

Concept

-^ R‐Format •^ Administrivia •^ I‐Format^ –^ Branching^ and

PC‐Relative^ Addressing

-^ J‐Format •^ Bonus:^ Converting

to^ Machine^ Code

Practice

6/27/^

Summer^2012 ‐‐^ Lecture^ #^

Administrivia

-^ HW^2 due^ Sunday •^ Project^1 due

7/8 – No homework^ next^ week – Will be released^ in^ the^ next^ two

days 6/27/^

Summer^2012 ‐‐^ Lecture^ #^