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The labbook requirements for ceg/ee 260 course. Students are expected to maintain an accurate and complete labbook reflecting their work, including all design processes, circuit designs, simulation/test results, and assumptions. Proper labeling and documentation are essential for clear communication and future reference. Failure to follow these guidelines may result in deducted points.
Typology: Lab Reports
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CEG/EE 260 Labbook Policy Dr. Doom
The lab book for this course is the primary proof of a student's work. Therefore, it should be an accurate and complete document reflecting the student's effort. In addition, the purpose of the lab book is to get the student accustomed to proper design and documenta- tion practices. When a student enters the "real world", it is very likely that he/she will work on a project for some time and then move on to another project or company. Just because a given individual has left a project does not mean that the project disappears. Often a project will be maintained and updated for several years after it's initial release. Some unfortunate individual is usually left maintain- ing a project long after the original designers are gone. This person does not have to be so "unfortu- nate". His fate is determined by the documentation left by those that went before him. A well- documented project is fairly simple to take over, but a poorly documented project can be a nightmare. So, in an attempt to proliferate better documenta- tion practices, a reasonable effort will be expected of students in this course. It is well known that engi- neers typically hate to write documentation -- they like to design new and exciting things, but good documentation is often critical to the success of a project, both during the development phase and the maintenance phase. Documentation is especially important to you, be- cause if your TA cannot follow your work, points will be deducted. Try to be as clear and concise as possible. Act is if you are turning your lab book in to your boss. Your documentation is an important part in judging your overall skill and effort. That being said, it is understood that this is a col- lege course and students have many other require- ments on their time. Please do your best, and at a minimum, follow the subsequent guidelines.
1.) Show all of your work. Many students will do preliminary design work on scrap paper. The lab book is also made of paper, why not do your work there? Preliminary design is an important part of the process. Label your work as "preliminary" - incorrect initial approaches will not count against you. Some circuits are very simple and it is not necessary to show work. Some circuits are not so simple. If there is only a final print-out for a complex circuit, can you prove that it is your own work? Can you explain its operation? It is best to show your design process - then there is no question about a circuit's origins. 2.) Include printouts of all of your circuit designs.
In this course, we will use hierarchical design practices - this means that our final circuits will be composed of smaller sub-circuits. Include the print- outs of the smaller circuits so that person who re- views your schematics knows what the circuit does. You may know what is inside of a sub-circuit block, but without a printout, your TA will not.
3.) Always include printouts of your most recent circuits. The lab book is a living document of your design. It should eventually reflect the final circuit that you have designed (or are working on). It is not neces- sary to remove previous versions of your work from the lab book, just mark them as "old" or "outdated" and add the new designs to your book. This will help the person who follows you to understand your thinking process when learning the function of your circuit. It will also help you when you need to re- member why you made certain design decisions. Finally, note that your lab book is your emergency backup. If disaster strikes, and lose or corrupt your files, you will want your most recent fully debugged schematics available.
4.) Include simulation/test results for every circuit that you design. Anyone can throw logic gates and wires onto a schematic page. Simulation and testing are the proof that it works. Some circuits in this course are quite large and complex. If exhaustive testing is not feasi- ble, then please document the test cases that you performed. One of the most important aspects of engineering design is the development of adequate (and methodical) test procedures. A well thought out test plan shows thorough understanding of a design and its requirements.
5.) Present your test results in a clear and read- able way. Your TA will give you guidelines during your lab sessions.
6.) Document any assumptions that you make. If any portion of the lab assignment is unclear, then document what you believe the lab is specifying. It is best to clarify any doubts with your TA or professor, but this is not always possible -- especially when you start working on a lab assignment at 2:00 AM the morning the lab is due.
7.) Document any known bugs or problems. If the time has come to turn in your lab book and the circuit is not operating correctly, then document the problems that you are facing, the things that you have tried, and any ideas you have about fixing them.
CEG/EE 260 Labbook Policy Dr. Doom
It is difficult to admit to yourself that you are unable to complete your project on time, but documenting your known bugs is far better than having the TA discover them. Undocumented bugs in industry can result in lawsuits and lost jobs. Proper documenta- tion is looked upon favorably in this course - so do not be afraid to describe your problems.
8.) Label your Schematics. When drawing your schematics, it is in your best interest to label all nets (wires) in your design. Appropriate signal labeling also aids in the under- standing of circuit functionality. Label your cir- cuits... you will find it handy in debugging, your TA will find it useful in grading and understanding your work. Anyone who may pick up your design some- time in the future (including you) will also find it very beneficial. It is not really necessary to label some nets, (e.g. small nets between gates that implement a bigger function) but it is best to be generous with your labeling. Also it is sometimes very helpful to label a net in multiple places. If the signal is commonly used and travels great distances across the schematic page it is nice to have a label at locations where that signal is an input or output. Finally, make a strong attempt at maintaining a signal name throughout different levels of the design hierarchy.
Initially, it may seem as though there are many extra requirements being placed upon you in generating good design documentation. In the long run, you should find that these guidelines will help you to create better designs, and more importantly help you to create working designs. Many of these documen- tation practices will really make things easier as you work on more complicated designs. You may think that you have a good memory, but if you spend one or two days away from a project, it is amazing how much you can forget. Don't waste time figuring out what you did two days ago when it only takes a few seconds to write it down or print it out. Perhaps more immediately important, don't lose points for a poor lab book presentation when you have done the work!
Unless you are otherwise notified, your labbook containing your prelab for the week is due in the lab drop box at 5:00PM two days before your scheduled lab meeting. You can turn your lab book in early, but you will loose 2 points per day for lab books that are turned in late. Lab TAs can not accept work that is more than a week late. Such work will be given an automatic zero unless the course instructor approves late submission due to prolonged sickness or other documented emergency.
Final Note Additional guidelines and expectations may be required by your TA and presented during the in-lab session. Please make note of them. If you have any questions or concerns, please do not hesitate to ask.