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What is a program?
- A sequence of steps
- For each step, an arithmetic or logical operation is done
- For each operation, a different set of control signals is needed
Function of Control Unit
- For each operation a unique code is provided —e.g. ADD, MOVE
- A hardware segment accepts the code and issues the control signals
- We have a computer!
Components
- The Control Unit and the Arithmetic and Logic Unit constitute the Central Processing Unit
- Data and instructions need to get into the system and results out —Input/output
- Temporary storage of code and results is needed —Main memory
Computer Components: Top Level View
Execute Cycle
- Processor-memory —data transfer between CPU and main memory
- Processor I/O —Data transfer between CPU and I/O module
- Data processing —Some arithmetic or logical operation on data
- Control —Alteration of sequence of operations —e.g. jump
- Combination of above
Example of Program Execution
Instruction Cycle - State Diagram
Interrupts
- Mechanism by which other modules (e.g. I/O) may interrupt normal sequence of processing
- Program — e.g. overflow, division by zero
- Timer — Generated by internal processor timer — Used in pre-emptive multi-tasking
- I/O — from I/O controller
- Hardware failure — e.g. memory parity error
Transfer of Control via Interrupts
Instruction Cycle with Interrupts
Program Timing Short I/O Wait
Program Timing Long I/O Wait
Multiple Interrupts - Sequential
Multiple Interrupts – Nested
Time Sequence of Multiple Interrupts
Connecting
- All the units must be connected
- Different type of connection for different type of unit —Memory —Input/Output —CPU
Input/Output Connection(1)
- Similar to memory from computer’s viewpoint
- Output —Receive data from computer —Send data to peripheral
- Input —Receive data from peripheral —Send data to computer
Input/Output Connection(2)
- Receive control signals from computer
- Send control signals to peripherals —e.g. spin disk
- Receive addresses from computer —e.g. port number to identify peripheral
- Send interrupt signals (control)
CPU Connection
- Reads instruction and data
- Writes out data (after processing)
- Sends control signals to other units
- Receives (& acts on) interrupts
Buses
- There are a number of possible interconnection systems
- Single and multiple BUS structures are most common
- e.g. Control/Address/Data bus (PC)
- e.g. Unibus (DEC-PDP)
Address bus
- Identify the source or destination of data
- e.g. CPU needs to read an instruction (data) from a given location in memory
- Bus width determines maximum memory capacity of system —e.g. 8080 has 16 bit address bus giving 64k address space
Control Bus
- Control and timing information —Memory read/write signal —Interrupt request —Clock signals
Bus Interconnection Scheme
Big and Yellow?
- What do buses look like? —Parallel lines on circuit boards —Ribbon cables —Strip connectors on mother boards - e.g. PCI —Sets of wires
High Performance Bus
Bus Types
- Dedicated —Separate data & address lines
- Multiplexed —Shared lines —Address valid or data valid control line —Advantage - fewer lines —Disadvantages - More complex control - Ultimate performance
Bus Arbitration
- More than one module controlling the bus
- e.g. CPU and DMA controller
- Only one module may control bus at one time
- Arbitration may be centralised or distributed
Centralised Arbitration
- Single hardware device controlling bus access —Bus Controller —Arbiter
- May be part of CPU or separate
