FPGA Circuit Realization - Lab 13 | ECE 0501, Lab Reports of Electrical and Electronics Engineering

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FPGA Circuit

Realization

Lab 13

Date of Experiment: April 5, 2007

Date of Report: April 18, 2007

Christopher Ellis

Purpose: The purpose of this laboratory is to utilize the Arithmetic Logic Unit designed previously in Lab 12 and realize the entire circuit on a single chip known as a Field Programmable Gate Array. The simulated ALU, which is capable of performing a variety of logical and arithmetic functions on up to two 4-bit inputs, will now be downloaded to the FPGA as opposed to being constructed on the protoboard. The ALU will utilize a register file as its memory, containing four addresses, each of which will be capable of storing four bits (or one hexadecimal character) in its memory. The circuit will be able to store data into any of the four memory addresses, display the contents of the current register being input to the ALU, and perform functions on those contents. Since the ALU will be utilizing a single-bus architecture, the capability to “store” one of its two potential inputs becomes necessary. The output of the ALU will have the capability of being displayed and selected as an input to be stored in any given register. The circuit will first be designed and constructed using simulated components, and then will be programmed onto the FPGA.

The simulated circuit will be constructed using components of the Altera library, and analyzed via MAXPlus+ II wave form simulations. The components of the ALU to be analyzed include the input and output bits of the simulated ALU, in addition to a Clock, four bits of the ALU Function Select, the Cin and Mode inputs to the ALU, the contents of the register selected, the contents being passed through the Data Selector MUX, the value of the MUX selector itself, the contents leaving the A latch, Write-Enable, and the values of the Read-from and Write-to register selectors.

Finally, the components of the ALU system will be replaced with their created VHDL counterparts, be substituted into the schematic, and reprogrammed to the FPGA to check for functionality.

The overall intent of this laboratory is to implement the previously designed ALU system using the FPGA, and to learn how to write and incorporate VHDL into the circuit design schematic.

Procedure: The general design and layout of the ALU was taken directly from the previously performed Lab 12 and was used as a basis for replacing and reimplementing the ALU using the Field Programmable Gate Array ( ote: Specific details concerning the exact design of the Lab 12 schematic can be found in the Appendix). The schematic was copied into a new project file and the 7-segment LEDs were removed according to instruction. In addition to removing the LEDs, the 4-bit latch component of Lab 12 (originally containing two 7474 D flip-flops) was replaced with a “4-bit latch” component. This 4-bit latch was created in a separate schematic by using four 1-bit “latch” (Altera library: name “latch”) components for each bit of the 4-bit input. The latches receive their input off of a 4-bit bus and are tied together synchronously with a single 1-bit “enable” signal. Their outputs are then tied to a 4-bit output bus and the latch system was compiled. A default symbol was created for this new 4-bit latch, and the symbol was inserted into the schematic in place of the previous latch. The simulated circuit was now to be prepared for

segment displays (see above) so the circuit was now ready to be tested according to the ALU functionality specifications and the proper sequence of control signal assertions (see Table 2 for brief addition example).

The underlying description of the ALU circuit consisting only of discrete logic blocks was now to have several components replaced with their VHDL equivalents. To get a feel for VHDL and its syntax, the first VHDL description to be created was to implement the BCD to 7-Segment LED decoder. This file, DispBin.vhd, has already been created but needed to be modified in order to produce the correct hexadecimal output for decimal values 10 through 15. Currently, an 8 bit string is used to identify the states of the seven LEDs in the display plus a decimal point. When the value entered into the decoder is equal to a of value 10, 11, 12, 13, 14, or 15, the LED displays the least significant value on the 7-segments and the lighted decimal point represents a number greater than 9. By changing the values of the 8 bits, the respective low-true inputs of the LED will be affected accordingly (see Figure 1). When the VHDL description was complete, a block symbol was created and used to replace the existing BCD to 7-segment decoders. The ALU was recompiled and simulated to display the modified BCD decode (see Figure 2). The 4x2to1 multiplexer was the next component of the ALU circuit to be implemented using VHDL. This architecture consisted only of a single “WHEN” statement, allowing the value at one input to be passed to the output at the discretion of the select bit (see Figure 3). The 4-bit latch was implemented by adding a variable signal to the architecture and using a “WHEN” statement to assign the value of the variable to the value of the data-in when the enable bit was equal to 1. The value of the variable was then sent to the output of the latch. With this implementation, the variable will always contain the value of the “latched” data until the enable signal is asserted again (see Figure 4). The final component to be written in the VHDL language is the 2-bit UP counter. This description was achieved by creating a variable within the architecture block and incrementing it every time the UP signal was asserted. In order to produce the proper two 1-bit output sequence from 0 to 3, the MOD operator was used to reduce the incremented “count” value to a number within this limited sequence. Another MOD operation is assessed to compute the least significant bit of the output, and a simple divide operation is used to determine the most significant output bit (see Figure 5). After each modification, a simulation was run to check for any errors and none were found. The output waveform remained the same throughout each simulation (see Results).

IN_SEL to MUX Data_IN W_Up to select register (writing) W_En to write to register R_Up to select register (reading) L_En to store read value until The next value is ready IN_SEL to MUX next Data_IN W_Up to select register (writing) R_Up to select register (reading) F_input HLLH to add IN_SEL to MUX ALU output in W_UP to select register (writing) W_En to write to the register Table 2 – Two 1-bit addition sequence

Figure 1 – VHDL description for the modified BCD



7-segment decoder

Figure 2 – Resulting Waveform

Figure 5 – VHDL description for the two 2-bit binary UP counters

Results Figure 6 displays the output waveform generated by the MAXPlus+ II simulated circuit. Notice that the data is consistent with the design specifications. As the data is written to and read from each address, stored to the “A” latch, and output from the ALU, you can see in detail the arithmetic and logic functions being imposed upon the operands. This waveform was used to test the ALU circuit after every insertion of VHDL components, and the output signals appeared identical following every simulation.

Figure 6 – Two Arithmetic and two Logic functions being performed with replaced VHDL components

Conclusion Through the completion of this laboratory, the design of the Arithmetic Logic Unit was proved functional through use of the Field Programmable Gate Array. Lab 12 was used as the basis of the design for Lab 13. The overall functionality of the ALU demonstrated the fundamental function of memory and processing in computers, and the ability to input, store, retrieve and process data. The benefits the FPGA proved worthwhile, as this method yields fewer wiring errors, faster prototyping, and a less costly resolution of circuit implementation.

The VHSIC Hardware Description Language was learned and utilized to create the ALU circuit by a different process. VHDL permits technology independent design through support for top down design and logic synthesis. To move a design to a new technology you need not start from scratch or reverse-engineer a specification – instead you go back up the design tree to a behavioural VHDL description, then implement that in the new technology knowing that the correct functionality will always be preserved.

References

• Quad 2-Input Nand Gate IC data sheet
• 74LS193 4-bit UP/DOWN Bianry Counter data sheet
• 74LS247 BCD to 7-segment Decoder/Driver data sheet
• 74LS670 4x4 Register File data sheet
• 74LS181 Arithmetic Logic Unit data sheet
• 74157 Quad 2/1 Data Selector data sheet
• 7474 Dual D Flip Flop data sheet
• MAN71A 7-Segment LED Display/Anode data sheet
• www.tektronix.com/la
• http://www.doulos.com/knowhow/vhdl_designers_guide/benefits_of_using_vhdl/
• Dr. Levitan and ECE 0501 Teaching Assistants
• “Lab 7: Latches and Flip Flops” lab on http://www.engr.pitt.edu/electrical/faculty-staff/0501/web- docs/2007/spring/main.html
• “Lab 11: Register Files” lab on http://www.engr.pitt.edu/electrical/faculty- staff/0501/web-docs/2007/spring/main.html
• “Lab 12: ALU (Arithmetic and Logic Unit)” lab on http://www.engr.pitt.edu/electrical/faculty-staff/0501/web- docs/2007/spring/main.html
• “Lab 13: FPGA Circuit Realization” lab on http://www.engr.pitt.edu/electrical/faculty-staff/0501/web- docs/2007/spring/main.html
• “VHDL Notes” Slide show on http://www.engr.pitt.edu/electrical/faculty- staff/0501/web-docs/2007/spring/main.html