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Notes for Spring 2006 – Below is part of an old final exam. The emphasis with this course was somewhat different, so irrelevant material was removed. Expect additional material on:
1. As described before the 6 week exam (see calendar for Feb 13). In particular, you will need to **write MIPS code/functions.
- As described before the 12 week exam (see calendar for April 3)
- Since 12 weeks: Caching, Virtual Memory, Pipelining, Multiprocessors,** Ethics (Reverse Engineering & DMCA) – additional problems at end.
Also, you will be given the following possible useful information – you should familiarize yourself with it in advance:
- A copy of the single-cycle and multi-cycle datapaths are provided to you – see last page.
- For function calls: Integer values are passed in $a0, $a1, $a2, $a Floating point values are passed in $f12, $f Integer values are returned in $v Floating point values are returned in $f0.
- ALU control ALUOp = 00 ALU will Add ALUOp = 01 ALU will Subtract ALUOp = 10 ALU will perform action indicated by the instruction’s function field
- Single precision floating point numbers – bias is 127 Double precision floating point numbers – bias is 1023
SI232 Computer Architecture
PRACTICE Final Exam
Name ______________________________ Alpha ________________________ Section: 3001 5001 (circle one) Note: This exam is closed-book, closed-notes. No calculators are permitted. Leave answers in fractional form. To receive partial credit, show all work and make it legible.
Page 1 (10 Pts) ______________ Page 2 (6 Pts) ______________ Page 3 (10 Pts) ______________ Page 4 (17 Pts) ______________ Page 5 (18 Pts) ______________ Page 6 (11 Pts) ______________ Page 7 (14 Pts) ______________ Page 8 (7 Pts) ______________ Page 9 (7 Pts) ______________
TOTAL ______________
(1 pt) Define abstraction, with respect to its importance to computer architecture.
(5 pts) A compiler designer is trying to decide between two code segments for a particular machine. The hardware designers have provided the following data below about the CPI for each class, and the instruction counts being considered for each code sequence.
Class CPI for this instruction class A 2 B 3
How many cycles are required for each code sequence? Code sequence #1: Code sequence #2:
Which is faster and how by how much?
What is the CPI for each code sequence?
CPI for code sequence #1: CPI for code sequence #2:
(1 pt) Define Instruction Set Architecture.
(1 pt) List the five classic components of a computer.
(2 pts) Explain the stored-program concept.
Instruction Counts for Instruction Classes Code sequence A B 1 3 5 2 7 2
(1 pt) What does the MIPS register $ra hold? Why is it important?
(2 pts) Name the fields for R-format MIPS instruction and list their size (in bits).
(3 pts) List and provide a short description for the 3 pipelining hazards:
(2 pts) Fill in the following sentence: Pipelining improves the performance by instruction throughput, as opposed to the execution time of an individual instruction.
(3 pts) Show MIPS assembly code that would implement the following high level language code. Use the following register assignments: A is $t0, B is $t1, C is $t2, D is $t4, R is $v3.
A = B + C – D + R;
(3 pts) List 3 of the addressing modes utilized in MIPS.
(2 pts) List the 4 design principles associated with Instruction Set Architectures. Provide a brief explanation (or example) of each of them.
(Circle one) (1 pt) Floating point representation uses two’s complement representation T F
(1 pt) When the immediate constant is mapped T F to 32 bits, its value is
(1 pt) Overflow has occurred when adding two negatives yields a ___________ number.
(3 pts) Given that the base address of an array is stored in register $s5, and the size of each element is one word, show on the picture what will the following instruction do.
lw $t1, 16($s5)
(3 pts) Given the following bit pattern is a single precision floating point representation, what decimal number does it represent?
0011 1111 1111 0000 0000 0000 0000 0000
(2 pts) List 2 performance considerations for I/O systems.
$s
$t
10 20 30 40 50 60 70 80
10
increasing addresses
Main memory
(2 pts) What are the two writing strategies discussed in class/notes when there is a write “hit” in cache? Define each strategy.
(2 pts) Define spatial locality
(4 pts) Calculate the size of the tag and the size of the cache index and total number of bits is cache given that: Cache is direct mapped; Cache size = 8K; Block size = 4 bytes
Index size =
Tag size =
Total # of bits =
(1 pt) Explain why reduction / minimization is important:
(2 pts) How would decreasing the block size affect miss rate?
Extra Problems for Practice – only covers since 12 week exam
Many of these are “why” questions – you should also look at the in-class
Exercises for more practice problems.
1. What is the difference between a conflict miss and a compulsory miss? How would you reduce **each type?
- What are two different strategies for dealing with cache writes? What is an advantage and** **disadvantage of each type?
- Show the correct formula for calculating a cache index, given the following parameters:** a. N = 16, Block size = 4, Associativity = 4
b. N = 16, Block size = 8, direct-mapped
4. Suppose a direct-mapped cache has 64 blocks that are 8 bytes each. Show how to break the following address into the tag, index, & byte offset. 0000 1000 0101 1100 0001 0001 0111 1001
How does this change if the cache is 4-way set associative?
**5. Why might we want more than one level of a cache?
- Suppose we have a direct-mapped cache with 4 blocks of 2 bytes each. Label each of the following** references as a hit or miss: 7 10 13 6 10 15 6 8
7. Suppose a processor has a CPI of 3.0 given a perfect cache. If there are 1.4 memory accesses per instruction, a miss penalty of 20 cycles, and a miss rate of 5%, what is the effective CPI with the real cache? Show the formula with values filled in, you don’t have to actually complete the calculations. **8. What are two advantages of using virtual memory?
- What is a TLB? Why do we need it?
- What are two ways for the processor to send information to an I/O device? And 3 ways for an I/O** **device to send information to processor?
- What is RAID? Why would you want to use it?
- Which is usually faster – an asynchronous or a synchronous bus? Why would you ever use the** **slower type?
- How does pipelining improve performance?**
