Download Final Exam Solutions - Digital Integrated Circuits | ECE 4420 and more Exams Electrical and Electronics Engineering in PDF only on Docsity!
FINAL EXAMINATION - SOLUTIONS
(Average score = 68/100)
Problem 1 - (20 points – This problem is required)
a.) An interconnect line is 10 mm long and has a resistance of 54mΩ/μm and a capacitance
of 0.1fF/μm and is driven by a 2X inverter (an inverter with an 8λ PMOS and a 4λ NMOS
where λ = 0.1μm). What is the total delay of the circuit from the input of the inverter to the end of the interconnect line?
b.) Find the number of buffers (round off to the nearest integer) and the size of these buffers to minimize the delay of the 10 mm interconnect through buffer insertion.
c.) Since the X2 buffer probably cannot drive the insertion buffer at the input directly, use a fanout of 4 (FO4) to design a cascade of inverters that will allow the X2 buffer at the input to drive the first insertion buffer with minimum delay.
d.) For your design above which includes the cascade of inverters at the input followed by the buffer insertion in the 10 mm interconnect, compute the delay value from the 2X inverter at the input to the end of the interconnect. Assume that the average F04 delay of the cascaded inverters is 100ps.
Solution a.)
0.8μm
0.4μm
10mm R (^) wire = 540Ω and Cwire = 1pF
12.5kΩ/2=6.25kΩ
1.2fF 0.5pF 0.5pF
540 Ω
S04FES
τ ≈ (6.25kΩ)(0.5pF) + (6.79kΩ)(0.5pF) = 6.52ns
b.) Find the number of inserted buffers, N , and the size of each buffer, M.
N =
RwireCwire /
R (^) eqn ( C (^) J + C (^) G )(1+ β)
0.5·540·1pF 12.5kΩ(1fF·0.2·3+2fF·0.2·3)
270ps 22.5ps = 3.46^ ≈^3
M =
Reqn
C (^) G (1+ β)
C (^) int R (^) int =^
12.5kΩ 2fF·0.2·
0.1fF/μm 0.054Ω/μm
= 1.042x10 19 ·1.82x10 -15^ = 137.7 ≈ 140
c.) Find the number of cascaded inverters to go from X2 to X140 with a fanout of 4.
n =
ln( Cload / Cin ) ln f =
ln(140/2) ln4 = 3.06^ ≈^3
The design of the inverters driving and insertion buffers is shown below.
Problem 1 – Continued
c.) Continued.
x2 x8 x32^ x140^ x140^ x
mm 10 3
mm 10 3
mm Scaling up the drive Buffer Insertion S04FES1B
Note that for the optimum delay, the size of the buffer being driven by the X32 buffer should be X128. However, it has been increased to X140 to be the first insertion buffer. The alternative would be to use a different fanout or add another buffer which would increase the delay. We will assume the above design represents the best choice under the conditions given.
d.) The model one stage of the buffer insertion is given below.
R (^) X (^140) R (^) wire /
C (^) x 140 (out) C^ wire /6^ C (^) wire /6 C (^) x 140 (in)
10mm/
S04FES1C
R X 140 =
12.5K
140 = 90Ω,^ C^ X 140( out )^ = 140(3· W · C^ self ) = 140·3·0.4·1 = 168fF, C (^) X 140( in ) = 140(3· W · C (^) g ) = 140·3·0.4·2 = 336fF, C (^) wire = 1pF
The delay of the buffer insertion stage modeled above is,
τ buffer insertion + wire /3 = (90)(168fF + 167fF) + (90+180)((167fF + 336fF) = 166 ps
The delay of the design is expressed as
Delay = 3FO4 + 3(Buffer +
Wire 3 ) = 3·100ps + 3(166ps) = 798ps = 0.798ns
Problem 3 – (20 points – This problem is optional)
For the dynamic D-latch shown, compute the output
voltages at Q and Q for the given input when the CLK
goes high ( V (^) DD ). Assume 0.18μm CMOS technology,
W = L = 200nm, and V (^) DD = 1.8V. Use the velocity
saturation models for the transistors.
Solution
The first task is to find V (^) Q which is complicated by the
bulk-source voltage not being zero. We know that,
V (^) T = V (^) TO + γ V (^) SB + |2 φ F | - γ |2 φ F |
or V (^) Q = 1.8 – V (^) T = 1.8 – 0.5 - γ V (^) Q + |2 φ F | + γ |2 φ F |
V (^) Q = 1.3 – 0.3 V (^) Q + 0.84 + 0.3 0.84 = 1.575 - 0.3 V (^) Q + 0.
Solving by quadratic or iterating gives V (^) Q = 1.1516V ⇒ V (^) SG = 0.6484V
We see from this value that the PMOS is saturated and the NMOS is active. Therefore,
2 Wv (^) sat C (^) ox ( V (^) SG - 0.5) 2 ( V (^) S G - 0.5) + E (^) c L =^
W
L
μeC (^) ox
V Q
EcL
( V Q - V TO ) V Q -
V Q^2
V Q
2(0.2x10 -4^ )(8x10 6 )(0.648-0.5) (^2) (0.148 + 0.5)(270) = 0.652^ V^ Q^ -
V Q^2
V Q
1.2 (0.0259) = 0.652^ V^ Q^ -
V Q^2
2 →^ V^ Q^
2 -1.303 V
Q +0.052 = 0
V (^) Q = 0.6516 ± 0.5 1.303 2 - 4·0.052 = 0.6516 ± 0.0.6103 = 41mV
∴ V (^) Q = 41mV
CLK
V DD
V DD Q
Q
2W
W
S04FEP
Problem 4 – (20 points – This problem is optional)
Use 0.18μm technology for this problem.
(a.) For the NAND gate shown, size the transistors to deliver a switching threshold of VS = 0.75V. Place the device sizes
( W ) on the schematic in units of nanometers assuming L = 200nm. Choose the W such that R (^) pullup is the same as the
standard inverter.
(b.) The voltage transfer curve of this gate is shown below for various combination of inputs. Provide an explanation as to why this occurs. How would you adjust the expression of VS to account for this effect?
Solution
a.) V (^) S =
V (^) D D - | V (^) Tp | + χ V (^) Tn
1+χ
where χ =
μ (^) n W (^) n μ (^) p W (^) p
1.8-0.5+χ0. 1+χ
→ 0.75+0.75χ = 1.3 + 0.5χ
∴ 0.25χ = 0.55 → χ = 2.
χ^2 =
μ (^) n W (^) n μ (^) p W (^) p →^ 2.^
540 W (^) n 180 W (^) p →^
W (^) n W (^) p =
540 2.^
To get the standard pull-up resistance, Wp must be 400nm. Therefore,
W (^) p = 400nm and W (^) n = 1.613·400nm = 645nm
Another way to work this problem is to assume L (^) n = Lp = L. Therefore,
χ =
E (^) cp W (^) n E (^) cn W (^) p = 2^
W (^) n W (^) p = 2.2^ →^
W (^) n W (^) p = 1.
Choosing W (^) p = 400nm gives W (^) n = 484nm which are acceptable answers although slightly
different.
(b.) Compared with B , A moves to the left because of the body effect on the NMOS transistor.
With both inputs tied together the pull-down is weaker because neither input is at VDD initially.
A
B
Out
VDD
V (^) out S04FEP4A
V (^) in
Both inputs tied together
A
only
B only
S04FEP4B
Problem 6 – (20 points – This problem is optional)
A dynamic logic gate is shown. The pre-charge device has a W/L of 5, the n-channel devices have a W/L of 3, and inverter has a pull-up of 4 and a pull-down of 1. (a.) What is the logic function of the gate at the output of the inverter? (b.) Why is the output inverter skewed? (c.) Using the device sizes above, what is the logical effort of input B of the first stage of the domino logic (when its immediate output is falling), and the inverter (when its output is rising). Computer these two values separately.
A C
B D
E
φ
VDD
S04FEP
Solution
(a.) f = ( B + D )( A + C + E )
(b.) To make the risetime faster.
(c.) B input:
The W/L of each transistor is 3 times the minimum size so the resistance of each of these transistors is R /3. However, there are three of them in series in the pulldown path so the effective output resistance is 3 R /3 = R. The input capacitance is 5 times the minimum capacitance. Therefore,
LE B =
( R )(5 C (^) g ) 3 RC (^) g = 5/3^ →^ LEB^ = 5/
Inverter input:
For the standard inverter, the input capacitance is 3 Cg and the output resistance is R.
However, the pullup is twice as big as usual so its output resistance is R /2 instead of R. Therefore,
LE (^) inv =
( R /2)(5 C (^) g ) 3 RC (^) g = 5/6^ →^ LEinv^ = 5/
Problem 7 – (20 points – This problem is optional)
(a.) Estimate the worst-case fall propagation delay, t (^) PHL , for the circuits below. Assume
that each gate is only loaded by its own self-capacitance and a step function is applied at the inputs. The values beside each transistor are W/L ratios. Identify the fastest and slowest gate given these configurations. Assume that the channel length of all transistors is 0.2μm.
(b.) Now assume that there is a single 100fF loading of each of the gates above (and the self capacitances are now zero). Compute the tPHL delays for the gates and again identify
the fastest and the slowest gates.
A
V DD
V DD V DD
A
V DD
A
S04FEP
Solution
(a.)
Inverter: τ = 0.7 RC (^) inv = 0.7(12.5kΩ)(3)(0.2μm)(1fF/μm) = 5.25ps
NAND: τ = 0.7 RC (^) nand = 0.7(12.5kΩ)(8)(0.4μm)(1fF/μm) = 28ps
NOR: τ = 0.7 RC (^) nor = 0.7(12.5kΩ/2)(10)(0.4μm)(1fF/μm) = 17.5ps
Therefore the inverter is the fastest and the NAND gate the slowest.
(b.)
Inverter: τ = 0.7 RC (^) inv = 0.7(12.5kΩ)(100fF) = 875ps
NAND: τ = 0.7 RC (^) nand = 0.7(12.5kΩ)(100fF) = 875ps
NOR: τ = 0.7 RC (^) nor = 0.7(12.5kΩ/2)(100fF) = 438ps
Therefore the NOR is the fastest and the NAND gate and inverter the slowest.
