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Chapter 3
Field-Effect Transistors
Chapter Goals
Describe operation of MOSFETs and JFETs.
Define MOSFET characteristics in operation regions of cutoff,triode and saturation.
Discuss mathematical models for
i-v
characteristics of MOSFETs
and JFETs.
Introduce graphical representations for output and transfercharacteristic descriptions of electronic devices.
Define and contrast characteristics of enhancement-mode anddepletion-mode MOFETs.
Define symbols to represent MOSFETs in circuit schematics.
Investigate circuits that bias transistors into different operatingregions.
MOSFET and JFET DC circuit analysis
Explore MOSFET modeling in SPICE
Types of Field-Effect Transistors
MOSFET (Metal-Oxide Semiconductor Field-EffectTransistor)
- Primary component in high-density VLSI chips such
as memories and microprocessors
JFET (Junction Field-Effect Transistor)
- Finds application especially in analog and RF circuit
design
The MOS Transistor
Polysilicon
Aluminum
The NMOS Transistor Cross Section
n
areas have been doped with
donor
ions
(arsenic) of concentration N
D
are the majority carriers
p
areas have been doped with
acceptor
ions (boron) of concentration N
A
are the majority carriers
Gate oxide
n+
Source
Drain
p substrate
Bulk (Body)
p+ stopper
Field-Oxide
(SiO
2
)
n+
Polysilicon
Gate
L
W
MOS Capacitor Structure
First electrode
Gate
:
Consists of low-resistivitymaterial such as highly-doped polycrystalline silicon, aluminum or tungsten
Second electrode
Substrate or Body:
n
p
type semiconductor
Dielectric
Silicon dioxide
:
stable high-quality electricalinsulator between gate andsubstrate.
Substrate Conditions for Different
Biases
Accumulation
V
G
<< V
TN
Depletion
V
G
< V
TN
Inversion
V
G
> V
TN
N
-Channel
MOSFET
Current voltage
Characteristic
i
S
The Threshold Voltage
V
T
= V
T
F
+ V
SB
F
where
V
T
is the threshold voltage at V
SB
= 0 and is mostly a function of the
manufacturing process
- Difference in work-function between gate and substrate
material, oxide thickness, Fermi voltage, charge of impuritiestrapped at the surface, dosage of implanted ions, etc.
V
SB
is the source-bulk voltage
φ
F
= -
φ
T
ln(N
A
/n
i
) is the
Fermi potential
(
φ
T
= kT/q = 26mV at 300K is
the thermal voltage; N
A
is the acceptor ion concentration; n
i
≈
1.5x
10
cm
at 300K is the intrinsic carrier concentration in pure
silicon)
γ
=
√
(2q
ε
si
N
A
)/C
ox
is the
body-effect coefficient
(impact of changes in
V
SB
) (
ε
si
=1.053x
F/m is the permittivity of silicon; C
ox
=
ε
ox
/t
ox
is
the gate oxide capacitance with
ε
ox
=3.5x
F/m)
The Body Effect
0.
0.
0.
0.
0.
0.
0.
0.
0.
0.
0.
-2.
-
-1.
-
-0.
0
V
BS
(V)
V
SB
is the substrate
bias voltage (normallypositive for n-channeldevices with the bodytied to ground)
A negative bias
causes V
T
to increase
from 0.45V to 0.85V
It is to be noted that the V
DS
measured relative to the source
increases from
0 to V
DS
as we travel along the channel from
source to drain.
This is because the voltage between the gate
and points along the channel decreases from
V
GS
at the source
end to
V
GS
-V
DS
.
When V
DS
is increased to the value that reduces the voltage
between the gate and channel at the drain end to
V
t
that is ,
V
GS
-V
DS
=V
t
or
V
DS
= V
GS
-V
t
or V
DS
(sat)
≥
V
GS
-V
t
Concept of Asymmetric Channel
Transistor in Saturation Mode
S
D
B
G
V
GS
V
DS
> V
GS
- V
T
I
D
V
GS
T
n+
n+
Pinch-off
Assuming V
GS
> V
T
V
DS
The current remains constant (saturates).
n
-Channel
MOSFET
Current voltage
Characteristic
TN
GS
)
SAT
(
DS
V
v
v
v
DS
(sat)
is the
saturation or pinch-off voltage
TN
GS
DS
2
TN
GS
D
V v v V v L
W
2
' n
K
i
−
≥
−
=
for
by
v
G
μ
p
C
ox
)
Key design parameter
Channel-Length Modulation
As
v
DS
increases above
v
DSAT
the length of the
depleted channel beyondpinch-off point, DL,increases and actual Ldecreases.
i
D
increases slightly with
v
DS
instead of being
constant.
i
D
K
' n
W
L
v
GS
V
TN
λ
v
DS
channel length modulation
parameter
Example 5.
P
Key design parameter
Problem-Solving Technique:
nMOSFET
DC
Analysis
Assume the transistoris in
saturation
a.
V
GS
> V
TN
, I
D
V
DS
V
DS
(sat)
Analyze circuit usingsaturation I-V relations
TN
GS
DS
V
v
v
−
≤
TN
GS
DS
V
v
v
−
≥
TN
GS
V
v
≤
- Evaluate resulting bias condition of transistor
a. If
V
GS
< V
TN
, transistor is likely in
cutoff
b. If
V
DS
< V
DS
(sat),
transistor is likely in
nonsaturation
region
- If initial assumption is proven incorrect, make new assumption
and repeat Steps 2 and 3
MOSFET Circuit Symbols
g) and (i) are the
most commonly usedsymbols in VLSI logicdesign.
MOS devices aresymmetric.
In NMOS,
n
+
region at
higher voltage is thedrain.
In PMOS
p
+
region at
lower voltage is thedrain
Summary of the MOSFET
Current-Voltage relationship
Table 5.
MOSFET DC Analysis
• The DC circuit analysis is an important
part of the design of an amplifier.
Bias Analysis Approach
Assume a region of operation (generally thesaturation region)
Use circuit analysis to find
V
GS
Use
V
GS
to calculate
I
D
and
I
D
to find
V
DS
Check validity of operation region assumptions
Change assumptions
and analyze again if required.
NOTE: An enhancement-mode device with
V
DS
V
GS
is
always in saturation
Ex 3.
The transistor shown inFig. has parameters
V
TN
2 V and
K
n
0.25 mA/V
If
V
DD
10 V,
R
k
R
160 k
, and
R
D
10 k
, find
I
D
V
DS
and
the power dissipation inthe transistor
Ex 3.
The transistor shown inFig. has parameters
V
TP
1.2 V and
K
P
mA/V
. If
V
DD
10 V,
R
//R
200 k
determine the circuitparameters such that
I
DQ
1.2 mA and
V
SDQ
4 V.
Ex 3.
The transistor shownin Fig. has parameters V
TP
-1 V and
K
P
0.25 mA/V
, find
V
SG
I
D
, V
SD.
if I
D
=
0
, V
DS
=
5 V
if V
DS
=
0
, I
D
=V
DD
/R
D
=
0.25 mA
Load Line
Ex 3.
The transistor shownin Fig. has parameters V
TP
-1 V and
K
P
0.25 mA/V
, determine
the transition pointparameters
Ex 3.
The transistor shown inFig. has parameters
V
TP
8 V and
K
P
mA/V
. Design the circuit
such that
I
D
A and
V
SD
8 V. Determine the
variation in Q-point if
K
P
parameter vary by ±5percent.
Problem-solving Technique :MOSFET DC Analysis
Bias Analysis Approach
Assume a region of operation (generally the saturation region)
Use circuit analysis to find
V
GS
Use
V
GS
to calculate
I
D
, and
I
D
to find
V
DS
Check validity of operation region assumptions.
Change assumptions and analyze again if required.
NOTE:An enhancement-mode device with
V
DS
=
V
GS
is always in
saturation
.
Inversion layerexist at zero
v
GS
Increased channelresistance
v
GS
causes
transistor off
V
2
: pinch-off voltage
n
-channel
JFET
Characteristics
P
GS
DS
V
v
v
GS
DS
v
v
P
GS
DS
V
v
v
−
=
V
P
= the pinchoff voltage
I
DSS
= saturation current when
v
GS
= 0 V
Ex 3.24(design problem)
The transistor shown
in Fig. has
V
P
-4 V
and
I
DSS
6 mA, and
λλλλ
= 0. Design the
circuit such that
I
DQ
2.5 mA
and
V
DS
V and the total powerdissipated in
R
1
and
R
2
is 2 mW
Design
example
Design 5.
P
k
D
D
D
S
D
DD
DS
R
R
R
R
I
V
V
V
2
2
GS
GS
TN
GS
D
V
V
V
V
k
I
V
2
2
1
2
R
V
V
R
R
R
V
V
V
V
G
DD
G
S
GS
G
k
k
1
2
R
R
