8-bit Signed Two’s Compliment Complex Multiplier VLSI ASIC for FFT Library, Study Guides, Projects, Research of Electrical and Electronics Engineering

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FFT Library: 8-bit Signed Two’s Compliment Complex

Multiplier VLSI ASIC

Team Members: David Schwarzenberg (lead) Shin Horiuchi Date: December 15, 2005 Class: ECE 715

Table of Contents:

FFT Library: 8-bit Signed Two’s Compliment Complex Multiplier VLSI ASIC............... 1 Final Pin Assignment:.................................................................................................... 17 What Was Learned:........................................................................................................ 18 References:..................................................................................................................... 19

List of Acronyms:

ADK Analog Design Kit ASIC Application Specific Integrated Circuit DA Design Architect DRC Design Rule Check FIFO First In First Out FFT Fast Fourier Transform IC Integrated Circuit LVS Logic Versus Schematic SDL Schematic Driven Layout VLSI Very Large Scale Integration

Implementation Overview:

The 8-bit signed two’s compliment complex multiplier contains both a complex adder and subtractor. A complex multiply is performed in the following manner:

 a^ ^ jb ^  c^ ^ jd^  ^ ac^ ^ bd^  ^ j bc ^  ad 

The real and imaginary parts of the output will be kept separate. This design requires four signed two’s compliment multiplies, as well as a signed two’s compliment adder and subtractor. The complex multiply will require the addition of a FIFO, at the beginning, to sample the inputs and at the end to sample the result of the complex multiply. The basic structure is as follows: Figure 2 : Block Diagram of Complex Multiplier The multiplier, adder and subtractor are all built using full and half adders. Half adders find the sum of two binary numbers and provide a sum and a carry. A full adder is similar to the half adder however, it has an input for a carry bit. Full and half adders can be constructed using logic gates, however, this is not the most efficient solution. The ADK library provides a full and half adder block. This block, much like the logic gates provided, has a layout already done. The ADK full adder block provided takes up approximately half the area of the logic gate implementation. The ADK full adder block uses 31% less power than a full adder implemented in logic gates. The delays of the two different full adders are very similar. The provided full adder in the ADK library will be used to implement the design. Figure 3 : ADK Half Adder and Full Adder An adder and a subtractor can be constructed using the full adder blocks. This is done using a ripple carry approach. A ripple carry adder computes the sum of the least significant bit first, then allows any carries to propagate to the next full adder. The sum of the first two bits is the least significant bit of the answer. The ripple carry subtractor

operates in a similar manner, however the two’s compliment of the second input must be taken. This is done by inverting the second input and setting the carry in high on the first full adder. This is the equivalent of taking the two’s compliment. The schematics are as follows: Figure 4 : Ripple Carry Adder (8-bit) Figure 5 : Ripple Carry Subtractor (8-bit) There are other ways to implement an adder or subtractor, such as a carry look ahead adder. However, the ripple carry adder and subtractor, implemented with the ADK full and half adders, will take up less layout space, and will be more power efficient. The design is also much simpler, especially for the subtractor. The multiplier is implement using an add and shift algorithm. Special care must be taken when designing the multiplier so that it properly handles signed two’s compliment numbers. Because of the nature of signed two’s compliment numbers, no special consideration needed to be taken when creating the adder and subtractor. With the multiplier the sign bit must be properly dealt with or the multiplier will not function properly. The multiplier schematic is shown in Figure 6.

Figure 7 : FIFO using D latches with reset The FIFO is constructed using D flip-flops with a reset. This is a block that is included in the ADK library. The reset is needed so that the circuit can be put into a known state. The FIFO will sample and hold its input on the rising edge of the clock. A set of FIFO will be used on the input to sample and hold the inputted waveform. If the input is changing with time, it will confuse the complex multiplier. The FIFO will sample the input and hold it, until the complex multiplier is done calculating the answer. A set of FIFOs are also used at the output. There is a delay before the complex multiplier has computed the correct answer. The output FIFOs will sample and hold the output after this delay. This way the output is a discrete waveform, where all outputs change at the same time. This can be seen in the comparison of Figures 15 and 16. A timing diagram is provided below that illustrates the timing of the final circuit. Figure 8 : Timing diagram

In order to fulfill the specifications of the design, everything was wired according to Figure 2. The inputs are labeled A,B,C and D each with 4 bits. The outputs are 7-bits and are labeled J and R for imaginary and real, The full schematic is as follows: Figure 9 : Full Complex Multiplier

Testing the Design :

After completing the schematic, various simulations were run to verify the functionality of each design. Simulations were also used to determine the delays occurring within the circuit. Testing all input combinations is not always possible. Determining the most relevant test cases is important to confirm functionality and performance. In the simulation test runs pulsed waveforms were used to discover circuit delays.

Figure 11 : Ripple Carry Adder Simulation The case used to simulate the ripple carry adder is shown below. This case has the maximum number of carries. As seen in Figure 11 there is a delay propagating through the circuit as each carry takes place. The total delay time for the ripple carry adder in which the maximum number of carries is involved was seen to be less than 5ns. This is considered the worst case delay. 1 1 1 1 1 1 1 10101011 01010101 100000000

Figure 12 : Ripple Carry Subtractor Simulation The case used to simulate the ripple carry subtractor involves pushing all inputs from high to low. If the inputs are all high, the difference is zero thus the output would result would be all low. If the circuit is pushed from all high, to all low there will be a borrow across every full adder. This case would cause the maximum delay. The maximum delay for this worst case simulation is about 5.5ns.

Figure 14 : Un-clocked Complex Multiplier Simulation (no FIFO’s) Simulations were then run on the final schematic design without using FIFOs (un- clocked). Many simulations were run and the simulation shown in Figure 14 is just one of them. The delay in the final circuit are less than 8ns, much like the delay in this simulation, on output J6. The answer is for the imaginary part is 91(01011011) which comes from adding the two products of 77 and 76. The real part is 7(00000111) which comes from the difference of 77 and 76. The output of the un-clocked system is very

choppy and it is hard to read. The clocked version has a set of FIFOs on the output. The FIFOs will sample and hold after the correct amount of time to create an answer that is discrete, and easily readable. The same simulation is shown below in Figure 15. Both the imaginary and real components are easy to read. Figure 15 : Clocked Complex Multiplier Simulation

The blue, purple and grey represent different layers of metals in Figures 16 and 17. When metals on different layers cross they do not connect. This allows the crossing of paths, without shorting the design. In order to connect two layers, a via must be used. What is not shown in the layout are the poly, n-diff or p-diff areas. These are essential in forming transistors and are included in the layout. The final layout was 2048λ by 2056λ. For a 0.5micron process the design is 1.024mm by 1.028mm. This fits well into the 2mm squared specification and will allow plenty of room for routing. The final transistor count is 1802 CMOS transistors. The final step is to wire the layout into the pad. The pad is used to connect the actual transistors to the pins of the final chip. This connection is made with fine gold wires that are soldered onto each pad. The routing between the layout and each pad was performed by hand. All of the routing goes around the outside of the layout to help prevent shorts. The date and initials are written in metal 3, or the outermost layer. They should be visible on the final chip. The final design is checked with the DRC and LVS to ensure that it has no layout errors and that the layout matches the schematic. Figure 17 : Final layout, hand routed into the pad

Final Pin Assignment:

Figure 18: Final Pin Assignment and Pin layout

Expected Performance:

The simulated power consumption was 35nW when simulated using ELDO. This appears to be much too small. For a 5 volt input to Vdd, this means the circuit will only source 7nA of current. The circuit is expected to run at approximately 100MHz if a clock with a 75% duty cycle is used. The circuit takes approximately 7.5ns to compute an output. From the timing diagram in Figure 8 the positive pulse must be 7.5ns long. With the inverted clock controlling the output FIFO the delay between taking data in and sampling the output is 7.5ns. If the clock signal only goes low for 2.5ns, the total period is 10ns. This would be a clock speed of 100MHz. If the clock cannot have a duty cycle, the expected clock speed is 67MHz.

References:

Deepak Kumar Tala. Asic-World. http://www.asic-world.com/digital/index.html Oct 7, 2005. http://www.seas.upeen.edu/~ese201/lab/CarryLookAhead/CarryLookAheadF01.html Oct 7, 2005. “Multipliers.” Tima Laboratory. http://tima-cmp.imag.fr/~guyot/Cours/Oparithm/english/Multip.htm Nov 14, 2005. Bigelow, Ken. “Digital Logic.” Play-Hookey.com. http://www.play-hookey.com/digital/ Oct 12, 2005. “PROJECT ASSIGNMENT: FAST FOURIER TRANSFORM COMPONENTS.” Introduction to VLSI. http://www.ece.unh.edu/courses/ece715/proj_options.htm Sept 28, 2005 M.M. Mano, C.R. Kime. Logic and Computer Design Fundamentals: 2nd^ Edition Updated. New Jersey. Prentice-Hall Inc., 2001. N.H.E. Weste, D. Harris. CMOS VLSI Design: A Circuits and Systems Perspective. Boston. Pearson Education Inc., 2005.