Download EXPERIMENT 10 - Latches: SR & D-Type and more Summaries Logic in PDF only on Docsity!
EXPERIMENT 10
Latches: SR & D-Type
OBJECTIVES:
- Examine S-R, gated S-R, and gated D-type latches.
- Create the designs for the S-R, gated S-R, and gated D latches in schematic mode.
- Test the designs on the target board.
MATERIALS:
Xilinx Vivado software, student or professional edition V2018.2 or higher. IBM or compatible computer with Pentium III or higher, 128 M-byte RAM or more, and 8 G-byte Or larger hard drive. BASYS 3 Board.
DISCUSSION:
In this experiment, we will discuss sequential circuits. The main difference between combinational circuits and sequential circuits is that combinational circuits do not have memory elements. So the output of a combinatorial circuit depends only on the present inputs. But the output of a sequential circuit depends on the effects of prior inputs (the memory) as well as the present inputs. Latches are simple, but very important, class of memory elements.
S-R NOR Latch
The S-R NOR latch has two inputs: S and R ( SET and RESET ) and two outputs: Q and not Q. The Q is the normal output and not Q is the complemented output. Any latch has two states: SET and RESET ( CLEAR ). When Q = 1, we say the latch is in the SET state. When Q = 0, the latch is in the RESET state. Figure 11.1 shows the
construction of a NOR latch. (The notation S-C , SET & CLEAR , is sometimes used for SR latches.)
The truth table below (Table 11.1) describes the characteristics of this NOR latch.
A NOR latch has active-high inputs. When both inputs are low ( S =0, R =0), the output will not change. It is “latched”. Normally, one of the inputs in it could be set to high to “set” or “clear” the latch. Yet if both inputs are high ( S =1 and R =1), both outputs will be low, which is not valid since Q and not-Q should be opposites.
The SR NAND Latch
The truth table in Table 11.2 shows how the EN input controls when the latch can respond to the S-R inputs.
It could be found that the function of the EN input is to enable/disable the inputs S and R.
The Gated D Latch
The gated D latch (D for data) can be built by adding an inverter before each of the two inputs in a gated S-R latch. A gated D latch is also called a level-triggered D flip-flop ( D FF ). Its diagram is shown in Figure 11.3.
By examining the following truth table, we can see that a level-triggered D FF has a simple operation. The output Q simply follows the data input D when the enable input is activated. Q is latched when the enable is low. There is no invalid state in this latch.
3. Next, we need to add SR-NAND Latch as following to a new file:
4. Then, the simulation program similarly:
5. Do not forget to change simulation settings to srNand latch simulation. Simulation
results for NAND based latch should look similar to:
7. Compare the characteristics of the NOR latch with those of the NAND
latch and comment on the differences and similarities of these two latches.
Section II. The Gated SR and D Latches
- Write the following VHDL code for gated SR latch:
- Implement the simulation changing variables according to your needs to fill the truth table. You should see the simulation output as shown below.
- Fill the truth table:
- Implement the D latch with gate by writing the following code:
- Fill the truth table:
QUESTIONS
Draw the logic diagram for a gated S-R latch using only NAND gates.
How does the Gate or Enable inputs work in the gated latches?
If we want the enable input active low, what kind of modification(s) should be applied to the gated D latch? Draw the diagram.
How could you avoid the invalid state in an S-R latch?
