Embedded Systems: Understanding FPGAs, IP Cores, and Interface Types, Essays (university) of Computer System Design and Architecture

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Embedded Systems Embedded Systems

Basic Concepts Basic Concepts

Concepts

 (^) A Field Programmable Gate Array ( FPGA ) is an integrated circuit designed to be configured by the customer or designer after manufacturing.  (^) SOC (System on a Chip)  (^) SOPC (System on a Programmable Chip)  (^) SOPC Builder (System on a Programmable Chip Builder) is software made by Altera that automates connecting soft-hardware components to create a complete computer system that runs on any of its various FPGA chips.  (^) PSoC (Programmable System on Chip) is a family of integrated circuits made by Cypress Semiconductor. These chips include a CPU and mixed-signal arrays of configurable integrated analog and digital peripherals.

IP Cores

 (^) An IP (Intellectual Property) core is a block of logic or data that is used in making a field programmable gate array ( FPGA) or application-specific integrated circuit ( ASIC ) for a product. As essential elements of design reuse , IP cores are part of the growing electronic design automation ( EDA) industry trend towards repeated use of previously designed components. Ideally, an IP core should be entirely portable - that is, able to easily be inserted into any vendor technology or design methodology.

IP Cores

 (^) IP cores fall into one of three categories: hard cores , firm cores , or soft cores. Hard cores are physical manifestations of the IP design. These are best for plug-and-play applications, and are less portable and flexible than the other two types of cores. Like the hard cores, firm (sometimes called semi-hard ) cores also carry placement data but are configurable to various applications. The most flexible of the three, soft cores exist either as a netlist (a list of the logic gates and associated interconnections making up an integrated circuit ) or hardware description language (HDL) code.

Logic Elements (LEs)

Logic Elements (LEs)



The FPGA LUT (Look-Up Table) is a small

ROM with several address inputs and one

data output. A common size is 16x1 bit, it has

four inputs and one output. By setting the

proper bits in that ROM, it becomes any

desired Boolean logic function having up to

four inputs and one output. That's why it is

sometimes called a function generator.

Avalon Switch Fabric



Avalon switch fabric?

 (^) Nios II uses the Avalon switch fabric as the interface to its embedded peripherals. Compared to a traditional bus in a processor-based system, which lets only one bus master access the bus at a time, the Avalon switch fabric, using a slave- side arbitration scheme, lets multiple masters operate simultaneously.

Six different interface types

 (^) Avalon Memory Mapped Interface (Avalon-MM) - an address-based read/write interface typical of master–slave connections.  (^) Avalon Streaming Interface (Avalon-ST) - an interface that supports the unidirectional flow of data, including multiplexed streams, packets, and DSP data.  (^) Avalon Memory Mapped Tristate Interface - an address-based read/write interface to support off-chip peripherals. Multiple peripherals can share data and address buses to reduce the pin count of an FPGA and the number of traces on the PCB.  (^) Avalon Clock - an interface that drives or receives clock and reset signals to synchronize interfaces and provide reset connectivity.  (^) Avalon Interrupt - an interface that allows components to signal events to other components.  (^) Avalon Conduit - an interface that allows signals to be exported out at the top level of an SOPC Builder system where they can be connected to other modules of the design or FPGA pins.