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Eight Bit - Computer Engineering - Solved Exam, Exams of Computer Science

Main points of this past exam are: Eight Bit, Memory Systems, Computer Engineering, Memory Systems Built, Decoder Required, Chips Required, Capacity, Datapath Elements, Performing the Shift, Eight Bit Word

Typology: Exams

2012/2013

Uploaded on 04/08/2013

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ECE 2030 J Computer Engineering Fall 2002
4 problems, 5 pages Exam Three Solutions 21 November 2002
1
Problem 1 (3 parts, 28 points) Memory Systems
Imagine using a 16 Mbit DRAM organized as 2 million addresses of 8-bit words to build
memory systems. The following three parts consider memory systems built using this chip.
Part A (10 points) Consider a memory system organized as 16 million addresses of 16-bit words.
number of chips needed in one bank 2 chips/bank
number of banks for memory system 8 banks
number of bits in address 24 bits
memory decoder required (n to m)3-to-8 decoder
number of DRAM chips required 16 chips total
capacity (in Mbits) 256Mbits
Part B (10 points) Consider a memory system organized as 2 million addresses of 32-bit words.
number of chips needed in one bank 4 chips/bank
number of banks for memory system 1 bank
number of bits in address 21 bits
number of DRAM chips required 4 chips total
capacity (in Mbits) 64 Mbits
Part C (8 points) Consider a memory system with 3 chips per bank and a 2-to-4 memory
decoder.
number of addresses 8M addresses
size of a word 24 bits
capacity (in Mbits) 192 Mbits
Problem 2 (1 part, 12 points) Instruction Formats
Suppose a datapath has three operand busses (two source, one destination) and it has the
following I-type instruction format:
Opcode: 8 bits Destination register: 6 bits Source register: 6 bits Immediate: 12 bits
Determine the following parameters of this datapath.
maximum number of different opcodes 256
maximum number of registers in the register file 64
range of possible signed immediate values 2±K
minimum number of bits needed to specify an R-type instruction 26 bits
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4 problems, 5 pages Exam Three Solutions 21 November 2002

Problem 1 (3 parts, 28 points) Memory Systems

Imagine using a 16 Mbit DRAM organized as 2 million addresses of 8-bit words to build memory systems. The following three parts consider memory systems built using this chip.

Part A (10 points) Consider a memory system organized as 16 million addresses of 16-bit words. number of chips needed in one bank 2 chips/bank number of banks for memory system 8 banks number of bits in address (^) 24 bits

memory decoder required ( n to m ) 3-to-8 decoder number of DRAM chips required (^) 16 chips total

capacity (in Mbits) 256Mbits

Part B (10 points) Consider a memory system organized as 2 million addresses of 32-bit words. number of chips needed in one bank 4 chips/bank number of banks for memory system (^) 1 bank

number of bits in address 21 bits number of DRAM chips required 4 chips total capacity (in Mbits) (^) 64 Mbits

Part C (8 points) Consider a memory system with 3 chips per bank and a 2-to-4 memory decoder. number of addresses 8M addresses size of a word 24 bits

capacity (in Mbits) 192 Mbits

Problem 2 (1 part, 12 points) Instruction Formats Suppose a datapath has three operand busses (two source, one destination) and it has the following I-type instruction format: Opcode: 8 bits Destination register: 6 bits Source register: 6 bits Immediate: 12 bits Determine the following parameters of this datapath.

maximum number of different opcodes 256

maximum number of registers in the register file (^64)

range of possible signed immediate values ± 2 K

minimum number of bits needed to specify an R-type instruction 26 bits

4 problems, 5 pages Exam Three Solutions 21 November 2002

Problem 3 (2 parts, 30 points) Datapath Elements

Part A (12 points) For the eight bit word below, determine the result of a performing the shift operation specified. Each shift type should assume the same input value. Assume the shifter word width is eight bits.

Input Value: 1 0 0 0 1 1 0

Shift type Count Result

logical +3 0 0 0 1 0 0 0 1

logical -2 0 0 1 1 0 1 0 0

arithmetic +2 1 1 1 0 0 0 1 1

arithmetic -3 0 1 1 0 1 0 0 0

rotate +1 1 1 0 0 0 1 1 0

rotate -2 0 0 1 1 0 1 1 0

Part B (18 points) Assuming X controls S0 and Y controls S1, determine the input values (LF 3 - LF 0 ) that should be given to the logical unit multiplexer to produce the logical functions below.

X Y out 0 0 LF 0 1 0 LF 1 0 1 LF 2 1 1 LF 3

LF 3 LF 2 LF 1 LF 0 Logical Function

NOR

XNOR

X

0 0 1 1 Y

OR