Dynamic Scheduling-Advance Computer Architecture-Lecture Slides, Slides of Advanced Computer Architecture

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Today's Topics

Recap - Lecture 13 Dynamic Scheduling Tomasulo’s Approach Summary

Recap: Summary

Instruction Level Parallelism in Hardware or Software SW parallelism dependencies defined by program result in hazards if HW cannot resolve HW exploiting ILP works when dependence cannot be determined at run time

Recap …..Cont’d

Scoreboard …. Cont’d– Structural and data dependencies are checked at ID stage It facilitates out-of-order execution which results in out- of-order completion

Recap …..Cont’d

Recap …..Cont’d

Recap …..Cont’d

Recap …..Cont’d

Today's Topics

Recap - Lecture 13 Tomasulo’s Approach Scoreboard Vs. Tomasulo’s Approach Summary

Tomasulo's Algorithm Vs. Scoreboard Differences between IBM 360 & CDC 6600 ISA is:

- IBM has only 2 register specifiers / instr vs. 3 in CDC 6600 - IBM has 4 FP registers vs. 8 in CDC 6600

Tomasulo's Organization For Dynamic Scheduling

Components of Tomasulo's Structure Load Buffers have three functions:

• Hold components of effective address until it is computed
• Track outstanding Loads waiting on memory
• Hold the result of completed load waiting for CDB

Components of Tomasulo's Structure Store Buffers also have three functions:

• Hold components of effective address until it is computed
• Hold the destination memory address of outstanding store instructions
• Hold the address and value of store until the memory unit is available

Sequence of operations All the results from the FP units or the Load unit are placed on the Common Data Bus, which goes to the FP register file as well as to the RS and store buffers

Tomasulo's Algorithm Vs. Scoreboard Control & buffers distributed with Function Units (FU) in Tomasulo vs. centralized in scoreboard

- FU buffers called ―reservation stations‖; have pending operands