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This course focuses on quantitative principle of computer design, instruction set architectures, datapath and control, memory hierarchy design, main memory, cache, hard drives, multiprocessor architectures, storage and I/O systems, computer clusters. This lecture includes: Dynamic, Scheduling, Tomasulo, Function, Register, Scoreboard, Flags, Operation, Destination
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Recap - Lecture 13 Dynamic Scheduling Tomasulo’s Approach Summary
Instruction Level Parallelism in Hardware or Software SW parallelism dependencies defined by program result in hazards if HW cannot resolve HW exploiting ILP works when dependence cannot be determined at run time
Scoreboard …. Cont’d– Structural and data dependencies are checked at ID stage It facilitates out-of-order execution which results in out- of-order completion
Recap - Lecture 13 Tomasulo’s Approach Scoreboard Vs. Tomasulo’s Approach Summary
Tomasulo's Algorithm Vs. Scoreboard Differences between IBM 360 & CDC 6600 ISA is:
- IBM has only 2 register specifiers / instr vs. 3 in CDC 6600 - IBM has 4 FP registers vs. 8 in CDC 6600
Tomasulo's Organization For Dynamic Scheduling
Components of Tomasulo's Structure Load Buffers have three functions:
Components of Tomasulo's Structure Store Buffers also have three functions:
Sequence of operations All the results from the FP units or the Load unit are placed on the Common Data Bus, which goes to the FP register file as well as to the RS and store buffers
Tomasulo's Algorithm Vs. Scoreboard Control & buffers distributed with Function Units (FU) in Tomasulo vs. centralized in scoreboard
- FU buffers called ―reservation stations‖; have pending operands