DMA Protocol - Computer Architecture - Lecture Slides, Slides of Computer Architecture and Organization

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load [2], [9]

• Transfer contents of memory

location 9 to memory location 2.

• Illegal instruction

2

load r1, [9]

store r1, [2]

4

load r1, [6]

out r1, datap

5

I/O interface architecture

for a DMA device

Memory address Count Control

DMA sequencer

Bus control

I/O address decode

Packing, unpacking and buffering

address

Read, write

Complete

Bus request

Bus grant

Data

Device control

Device data

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DMA Protocol

2. The DMA starts operation by

getting control of the bus, transfers

the data when available and

generates next addresses until the

transfer is complete.

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DMA Protocol

A number of controllers may be

connected to one bus.

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3. Once DMA transfer is complete,

controller interrupts the processor

which then determines if the entire

operation is completed successfully

and becomes the bus master

DMA Protocol

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Single-bus detached DMA

CPU DMA

module

I/O … I/O^ Memory

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I/O bus

CPU DMA

module

Memory

I/O I/O … I/O

I/O bus

System bus

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DMA

An I/O device transfers data at a rate of 10MB/s

over a 100MB/s bus. The data is transferred in

4KB blocks. If the processor operates at

500MHz, and it takes a total of 5000 cycles to

handle each DMA request, find the fraction of

CPU time handling the data transfer with and

without DMA

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Solution

With DMA

time required in handling each DMA request

is 5000 cycles. Since 2500 DMA requests

are issued (10MB/4KB) the total time taken

is 12,500,000 cycles. As the CPU clock is

500MHZ, the fraction of CPU time spent is

12,500,000/(500x106)^ or 2.5%.

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Example

A hard drive with a maximum transfer rate of

1MB/s is connected to a 32-bit, 10 MIPS CPU

operating at a clock frequency of 100

MHz.Assume that the I/O interface is DMA based

and it takes 500 clock cycles for the CPU to set-

up the DMA controller. Also assume that the

interrupt handling process at the end of the DMA

transfer takes an additional 300 CPU clock

cycles. If the data transfer is done using 2 KB

blocks, calculate the percentage of the CPU time

consumed in handling the hard drive.

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Cycle Stealing

The DMA module takes control of the bus

to transfer data to and from memory.

• it can either use the bus while the CPU is

not using it.

• or it can force the CPU to temporarily

suspend its operation.

The latter approach is called cycle stealing

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DMA and Interrupt breakpoints

during an instruction cycle

Instruction cycle

Fetch Instruction

Decode Instruction

Fetch Operand

Execute Instruction

Store Result

Process Interrupt

Processor Cycle

Processor Cycle

Processor Cycle

Processor Cycle

Processor Cycle

Processor Cycle

DMA

Breakpoints

Interrupt Breakpoint