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Digital Processor - Linear Control Systems II- Past Exam Paper, Exams of Linear Control Systems

National Center For Biological Sciences Linear Control Systems

Main points of this past exam are: Phase-Lead Compensator, Transfer Function, Digital Control System, Phase Lag Introduced, Bode Plot, Frequency, Maximum Phase-Lead, Resonant Frequency, Digital Processor, Programmed

Typology: Exams

2012/2013

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EE437 Linear Control Systems II Page 1 of 5

Semester Two Examinations 2011/2012

Exam Code(s)

4BEE

Exam(s)

Fourth Year Sports & Exercise Engineering

Module Code(s)

EE437

Module(s)

Linear Control Systems II

Paper No.

Repeat Paper

External Examiner(s)

Prof. G. W. Irwin

Internal Examiner(s)

Prof. G. Ó Laighin

Dr. Maeve Duffy

Instructions:

Answer any three questions from four.

All questions carry equal marks (20 marks).

Duration

2 hours

No. of Pages

Discipline

Electrical & Electronic Engineering

Course Co-ordinator(s)

Dr. Maeve Duffy

Requirements:

MCQ

Handout

Statistical Tables

Graph Paper

Log Graph Paper

Other Material

Partial preview of the text

Download Digital Processor - Linear Control Systems II- Past Exam Paper and more Exams Linear Control Systems in PDF only on Docsity!

Semester Two Examinations 2011/

Exam Code(s) 4BEE

Exam(s) Fourth Year Sports & Exercise Engineering

Module Code(s) EE

Module(s) Linear Control Systems II

Paper No. 1

Repeat Paper No

External Examiner(s) Prof. G. W. Irwin

Internal Examiner(s) Prof. G. Ó Laighin

Dr. Maeve Duffy

Instructions: Answer any three questions from four.

All questions carry equal marks (20 marks).

Duration 2 hours

No. of Pages 5

Discipline Electrical & Electronic Engineering

Course Co-ordinator(s) Dr. Maeve Duffy

Requirements :

MCQ

Handout

Statistical Tables

Graph Paper

Log Graph Paper

Other Material

The following standard formulas are given and may be freely used:

M (^) p M (^) o

ω r =ω n 1 − 2 ζ 2 ( ζ ≤ 0. 707)

ω d =ω n 1 −ζ 2

ω (^) b =ω (^) n (1− 2 ζ 2 ) + (1− 2 ζ 2 ) + 1

Tr (0 − 95%) ≅ 3 / ω b ( ζ > 0. 4)

T (^) r (0 − 100%) =

π − sin−^1 1 −ζ 2

ω n 1 −ζ 2 ( ζ < 1)

Overshoot = 100 exp −

T (^) s (±2%) ≤

ζ ω n

^ ( ζ < 1)

T (^) s (±5%) ≤

ζ ω n

^ ( ζ < 1)

Ziegler-Nichols Rules : Proportional control : K = 0.5 K c

P+I control : K = 0.45 K c , T i = 0.83 T c

PID control: K = 0.6 K c , T i = 0.5 T c , T d = 0.125 T c

Question 1

A phase-lead compensator with the transfer function

s 6

3 (s 2 ) G (^) c (s)

= has been designed to offset the

phase lag introduced by a D/A converter in a digital control system.

(a) Explain the main advantage of phase-lead compensation over P+D action in feedback

control systems. [3 marks]

(b) Sketch the Bode plot for the given phase-lead compensator, showing calculated values for

the maximum phase-lead introduced and the frequency at which maximum phase-lead is

found. [10 marks]

(c) Given that the phase-lead compensator was designed to fully compensate the maximum D/A

converter delay at the resonant frequency in this case: [7 marks]

(i) Calculate the sampling interval, T, of the D/A converter.

(ii) For a sampling interval equal to half that found in part (i), calculate the value to

which r can be reduced in the phase-lead compensator, while providing the same

level of compensation.

Question 2

The system shown in Fig. 1 includes a digital processor which is programmed with the algorithm,

m(k) = m(k-1)+2.75e(k)–1.25e(k-1).

The sampling period of the D/A converter, T, is 0.5 s.

Fig. 1

(a) Write an expression for the z-transform of the digital processor, Gc (z). [3 marks]

(b) Represent the system in the z-domain and write an expression for the closed-loop z-transfer

function, C(z)/R(z). [10 marks]

(c) Write the recursive equation relating sampled values of the output, c(k), to sampled

values of the input, r(k) , and determine the steady-state value of the output for a unit step

input. [7 marks]

Digital processor

D/A

A/D

r(kT) m(kT)^

m(t) c(t)

c(kT)

(s 0. 5 )^2

s

Question 3

The z-domain block diagram of a digital control system with sampling interval, T = 0.1 s, is given in

Fig. 2.

Fig. 2

(a) Write an expression for the closed-loop z-transfer function in terms of the parameters K and

α. If it is required to have conjugate poles at z = + 0.85 ± j0.25, choose suitable values for K

and α, and find the location of the remaining closed-loop pole. [8 marks]

(b) Map all poles and zeros of the closed-loop z-transfer function into the primary strip in the s-

plane. [6 marks]

(c) Based on the pole locations in the primary strip alone, predict the step-response overshoot

and explain why you would expect your prediction to be accurate. [6 marks]

Question 4

The P+I controller shown in Fig. 3 is to be replaced with a digital controller.

Fig. 3

(a) Write an expression for the closed-loop transfer function of the analogue system in the s-

domain and determine the locations of the closed-loop poles. [4 marks]

(b) Suggest with justification a suitable sampling interval, T, for a replacement digital

controller. [4 marks]

(c) Taking T = 0.5 s, use direct application of the bilinear transformation to define the z-

transform of a replacement digital controller. Write the corresponding computer algorithm to

be programmed into the digital processor. [7 marks]

(d) Give and explain two reasons why the stability of the digital controller of part (b) is likely to

be less than that of the analogue controller. Suggest one solution for improving the match

between analogue and digital controller solutions in this case. [5 marks]

C(s)

10 ( s+ 2 )

R(s)^ + (s 1 )(s 2 )

E(s)^ M(s)

C(z)

z 1

K(z ) −

−α R(z)^ + z 1. 4 z 0. 45

E(z)^ M(z)

Digital Processor - Linear Control Systems II- Past Exam Paper, Exams of Linear Control Systems

Related documents

Partial preview of the text

Download Digital Processor - Linear Control Systems II- Past Exam Paper and more Exams Linear Control Systems in PDF only on Docsity!

Semester Two Examinations 2011/

Exam Code(s) 4BEE

Exam(s) Fourth Year Sports & Exercise Engineering

Module Code(s) EE

Module(s) Linear Control Systems II

Paper No. 1

Repeat Paper No

External Examiner(s) Prof. G. W. Irwin

Internal Examiner(s) Prof. G. Ó Laighin

Dr. Maeve Duffy

Instructions: Answer any three questions from four.

All questions carry equal marks (20 marks).

Duration 2 hours

No. of Pages 5

Discipline Electrical & Electronic Engineering

Course Co-ordinator(s) Dr. Maeve Duffy

Requirements :

MCQ

Handout

Statistical Tables

Graph Paper

Log Graph Paper

Other Material

The following standard formulas are given and may be freely used:

ω r =ω n 1 − 2 ζ 2 ( ζ ≤ 0. 707)

ω d =ω n 1 −ζ 2

Tr (0 − 95%) ≅ 3 / ω b ( ζ > 0. 4)

ω n 1 −ζ 2 ( ζ < 1)

ζ ω n

^ ( ζ < 1)

ζ ω n

^ ( ζ < 1)

Ziegler-Nichols Rules : Proportional control : K = 0.5 K c

P+I control : K = 0.45 K c , T i = 0.83 T c

PID control: K = 0.6 K c , T i = 0.5 T c , T d = 0.125 T c

Question 1

A phase-lead compensator with the transfer function

= has been designed to offset the

phase lag introduced by a D/A converter in a digital control system.

(a) Explain the main advantage of phase-lead compensation over P+D action in feedback

control systems. [3 marks]

(b) Sketch the Bode plot for the given phase-lead compensator, showing calculated values for

the maximum phase-lead introduced and the frequency at which maximum phase-lead is

found. [10 marks]

(c) Given that the phase-lead compensator was designed to fully compensate the maximum D/A

converter delay at the resonant frequency in this case: [7 marks]

(i) Calculate the sampling interval, T, of the D/A converter.

(ii) For a sampling interval equal to half that found in part (i), calculate the value to

which r can be reduced in the phase-lead compensator, while providing the same

level of compensation.

Question 2

The system shown in Fig. 1 includes a digital processor which is programmed with the algorithm,

m(k) = m(k-1)+2.75e(k)–1.25e(k-1).

The sampling period of the D/A converter, T, is 0.5 s.

Fig. 1

(a) Write an expression for the z-transform of the digital processor, Gc (z). [3 marks]

(b) Represent the system in the z-domain and write an expression for the closed-loop z-transfer

function, C(z)/R(z). [10 marks]

(c) Write the recursive equation relating sampled values of the output, c(k), to sampled

values of the input, r(k) , and determine the steady-state value of the output for a unit step

input. [7 marks]

D/A

A/D

r(kT) m(kT)^

(s 0. 5 )^2

s

Question 3

The z-domain block diagram of a digital control system with sampling interval, T = 0.1 s, is given in

Fig. 2.

Fig. 2

(a) Write an expression for the closed-loop z-transfer function in terms of the parameters K and

α. If it is required to have conjugate poles at z = + 0.85 ± j0.25, choose suitable values for K

and α, and find the location of the remaining closed-loop pole. [8 marks]

(b) Map all poles and zeros of the closed-loop z-transfer function into the primary strip in the s-

plane. [6 marks]

(c) Based on the pole locations in the primary strip alone, predict the step-response overshoot