SWE1003-DIGITAL LOGIC AND MICROPROCESSER
NAME:HOSAMANE VEERATEJA
REG.NO:19MIS0204
SLOT:L19+L20
1)Verification of logic gates
OR GATE
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Digital logics and design lab, Assignments of Digital Logic Design and Programming
Lab digital assignment 2 nd year in multisim
Typology: Assignments
2019/2020
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SWE1003-DIGITAL LOGIC AND MICROPROCESSER
NAME:HOSAMANE VEERATEJA
REG.NO:19MIS
SLOT:L19+L
1)Verification of logic gates OR GATE
AND GATE
NAND GATE
ENOR GATE
b)X’+XY=X’+Y X Y X’ XY X’+XY X’+Y 0 0 1 0 1 1 0 1 1 0 1 1 1 0 0 0 0 0 1 1 0 1 1 1