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Publication# Issue Date: June 1993 90000 Rev. A Amendment /0 6-
Logic Reference Guide
Advanced
Micro
Devices
INTRODUCTION
Throughout this data book and design guide we have assumed that you have a good working knowledge of logic. Unfortunately, there always comes a time when you are called on to remember something which can only be found in that logic textbook which you threw away years ago.
This section is intended to provide a quick review and reference of the basic principles of digital logic. We will cover three general areas:
Basic logic elements Basic storage elements Binary numbers
Throughout the text, we will use the notation that was used throughout this book. If you are unfamiliar with the syntax, you will probably find it easy to understand as you read; if you wish for a more detailed explanation of the symbols, please refer to the Basic Design with PLDs section where they are defined.
As this is a logic reference only, we cannot take on lengthy discussions, nor can we train you in the basic principles of digital logic if you have not previously been trained. In such a case, we must refer you to your favorite logic textbook.
BASIC LOGIC ELEMENTS
In this section, we will discuss the concepts surrounding combinatorial logic functions.
The Three Basic Gates
There are three basic logic gates from which all other combinatorial logic functions can be generated. These functions areNOT,AND, andOR. A truth table indicat- ing these functions is shown in Table 1. Since they can be used to generate any function, they are said to be functionally complete.
Table 1. Truth Table for the NOT, AND, and OR Functions A B /A AB A+B* 0 0 1 0 0 0 1 1 0 1 1 0 0 0 1 1 1 0 1 1
The standard schematic symbols used to represent these gates are shown in Figure 1.
NOT
AND
OR 90000A-
Figure 1. Schematics Symbols for the Three Fundamental Gates
The AND and NOT functions can be combined into the NAND function. This is equivalent to an AND gate fol- lowed by an inverter, as shown in Figure 2a. Likewise, the OR and NOT gates can be combined into theNOR function, as shown in Figure 2b. Each of these gates is functionally complete; any logic function can be ex- pressed solely as a function of NAND or NOR gates.
a. The NAND Function
b. The NOR Function 90000A-
Figure 2. The NAND and NOR Functions
Precedence of Operators
Logic functions may be created with any combination of the three basic functions. How those functions are ex- pressed affects the evaluation of the function. The normal order of evaluation is:
NOT, AND, OR
Evaluation proceeds in order from left to right.
6-4 Logic Reference Guide
This order may be altered by inserting parentheses in the function. The contents of the parentheses will al- ways be evaluated before the rest of the expression, from left to right.
Some example functions are evaluated in Table 2.
Table 2. Using Parentheses to Change the Order of Evaluation AB+/A AB+/A A(B+/A) A(B+/A) A B C D C+D (C+D) C+D (C+D)** 0 0 0 0 0 0 0 0 0 1 1 0 1 1 0 0 1 0 0 1 1 0 1 0 1 1 1 1 1 1 1 1
Commutative, Associative, and
Distributive Laws
The AND and OR functions are commutative and asso- ciative. This means that the operands can appear in any order without affecting the evaluation of the function. This is illustrated in Tables 3 and 4.
Table 3. Commutativity A B AB BA A+B B+A** 0 0 0 0 0 0 0 1 0 0 1 1 1 0 0 0 1 1 1 1 1 1 1 1
Table 4. Associativity A B C (AB)C A(BC) (A+B)+C A+(B+C)** 0 0 0 0 0 0 0 0 1 1 0 0 1 1 1 0 1 0 0 1 1 1 1 1 1 1 1 1
There are actually two distributive laws; one of them re- sembles standard algebra more than the other. These two laws state that:
A(B+C) = (AB) + (AC) A+(BC) = (A+B) * (A+C)
Duality
The two distributive laws give an example of the concept ofduality. This principle states that:
Any identity will also be true if the following substitutions are made:
Thus, it is only necessary to prove the first of the distribu- tive laws; the second one will then be true by duality. Note that duality is not required to prove the second law; it can also be proven by truth table or by logic manipulation.
Manipulating Logic
Logic functions may be manipulated by the use of Boolean algebra. The logic functions may be expressed in one of the two canonical forms, or by using a simpli- fied expression.
6-6 Logic Reference Guide
b. The Sum-of-Minterms Expression c. The Product-of-Maxterms Expression
Minterm/ Maxterm A B C D X Y Number 0 0 0 0 1 1 0 0 0 0 1 0 1 1 0 0 1 0 1 1 2 0 0 1 1 1 1 3 0 1 0 0 0 1 4 0 1 0 1 1 0 5 0 1 1 0 0 0 6 0 1 1 1 1 1 7 1 0 0 0 1 1 8 1 0 0 1 1 1 9 1 0 1 0 0 0 10
....... ....... ....... 1 1 1 1 0 0 15
X = m0+m2+m3+m5+m7+m8+m = ∑m (0,2,3,5,7,8,9)
= /A * /B * /C * /D ;m
- /A * /B * C * /D ;m
- /A /B C * D;m
- /A * B * /C * D ;m
- /A * B * C * D ;m
- A * /B * /C * /D ;m
- A /B /C * D;m
Y = m0+m1+m2+m3+m4+m7+m8+m = ∑m (0,1,2,3,4,7,8,9)
= /A * /B * /C * /D ;m
- /A /B /C * D;m
- /A /B C * /D;m
- /A /B C * D;m
- /A * B * /C * /D ;m
- /A * B * C * D ;m
- A /B /C * /D;m
- A /B /C * D;m
X = M1M4M6M10M11M12M13M14M
ΠM (1,4,6,10,11,12,13,14,15)
=(A+B+C+/D) ;M
*(A+/B+C+D) ;M
*(A+/B+/C+D) ;M
*(/A+B+/C+D) ;M
*(/A+B+/C+/D) ;M
*(/A+/B+C+D) ;M
*(/A+/B+C+/D) ;M
*(/A+/B+/C+D) ;M
*(/A+/B+/C+/D) ;M
Y = M5M6M10M11M12M13M14*M
= ΠM (5,6,10,11,12,13,14,15)
=(A+/B+C+/D) ;M
*(A+/B+/C+D) ;M
*(/A+B+/C+D) ;M
*(/A+B+/C+/D) ;M
*(/A+/B+C+D) ;M
*(/A+/B+C+/D) ;M
*(/A+/B+/C+D) ;M
*(/A+/B+/C+/D) ;M
a. Truth Table
Figure 3. Finding the Canonical Form from the Truth Table
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Table 6. Conversion of Forms Table
Minterm Maxterm Inverted Minterm Inverted Maxterm Expansion of F Expansion of F Expansion of F Expansion of F Minterm – Maxterm numbers List Minterms not Maxterm numbers expansion are those numbers present in F are the same as of F not in the Minterm Minterm numbers list of F of F Maxterm Minterm numbers – Minterm numbers expansion are those numbers are the same as List Maxterms not of F not on the Maxterm Maxterm numbers present in F list of F of F
Desired Form Given Form
Simplifying Logic
Canonical forms are convenient in that it is easy to de- rive and convert them. However, the representation is bulky, since all variables must appear in each sum or product. These expressions can be simplified by apply- ing the basic laws and theorems of Boolean algebra.
There are four basic postulates, two of which are the commutative and distributive laws which were dis- cussed above. From these postulates, it is possible to derive nine basic theorems. The postulates and theo- rems are listed in Table 7.
Table 7. Postulates and Theorems of Boolean Algebra Postulate 1 (A) X + FALSE = X (B) XTRUE = X Postulate 2 (A) X + /X = TRUE (B) X * /X = FALSE Postulate 3 (A) X + Y = Y + X (B) XY = YX Postulate 4 (A) X * (Y + Z) = (XY) + (XZ) (B) X + (YZ) = (X + Y) * (X + X) Theorem 1 (A) X + X = X (B) X * X = X Theorem 2 (A) X + TRUE = FALSE (B) XFALSE = FALSE Theorem 3 / (/X) = X Theorem 4 (A) X + (Y + Z) = (X + Y) + Z (B) X * (YZ) = (XY) * Z Theorem 5 (A) / (X + Y) = /X * /Y (B) / (X * Y) = /X + /Y Theorem 6 (A) X + (X * Y) = X (B) X * (X + Y) = X Theorem 7 (A) (XY) + (X/Y) = X (B) (X + Y) * (X + /Y) = X Theorem 8 (A) X + (/XY) = X + Y (B) X * (/X + Y) XY Theorem 9 (A) (XY) + (/XZ) + (YZ) = (XY) + (/XZ) (B) (X + Y) * (/X + Z) * (Y + Z) = (X + Y)*(/X + Z)
Notice that each theorem and postulate (with the excep- tion of theorem 3) has two forms. This is a result of the duality principle; once one form of a theorem is estab- lished, the dual representation follows immediately. Theorem 3 has no dual because it does not involve any of the elements that have duals (+, *, 1, or 0).
As the logic expression is simplified, it no longer con- tains minterms (or maxterms), since some of the minterms and literals are being eliminated. What was a sum-of-minterms (product of maxterms) representation is now simplified to a sum-of-products (product of sums).
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90000A-
/A/B/D (^) /A/C/D
A A/C/D C B D
00
01
11
10
(^1 0 1 1) B/CD
0 1 1 0
0 0 0 0
1 1 0 0
00 01 11 10
A C B D
00
01
11
10
1 1 1 1
1 0 1 0
0 0 0 0
1 1 0 0
00 01 11 10
/A*/D
/C*/D
AB/C
/A/B/C
X = /A/B/D
Y = /A*/D
X Y
Figure 5. Using a K-map to Minimize the Functions in Figure 3
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A*C
A AB/C*/D C B D
00
01
11
10
1 0 1 1
0 1 1 0
0 0 0 0
1 1 0 0
00 01 11 10
A C B D
00
01
11
10
1 1 1
1 0 1 0
0 0 0 0
1 1 0 0
00 01 11 10
/ABD
A/BD
C*D
/X = C*D
/Y = C*D
X Y
A*C
/B*D
C*D
1
Figure 6. Finding Inverse Functions
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Comparison and Equivalence: the XOR
and XNOR Gates
The Exclusive-OR (XOR) and Exclusive-NOR (XNOR) gates are two special gates which are relatively com- mon. These gates have schematic symbols as shown in Figure 7a. They are actually compound gates, and can be generated by AND, OR, and NOT gates using the functions:
x :+: y = x/y + /xy ;XOR gate x :: y = xy + /x*/y ;XNOR gate
The XOR and XNOR functions are actually inverses of each other; that is,
x :+: y = /(x :*: y)
The truth tables for these gates are shown in Figure 7b. Note that the XOR function is true if and only if the oper- ands are different. For this reason, it is useful as a comparator. The XNOR function is true if and only if its operands are the same; therefore it is used as an equivalence indicator.
XOR
XNOR
a. Schematic Symbols
A B A:+:B A::B* 0 0 0 1 0 1 1 0 1 0 1 0 1 1 0 1
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b. XOR and XNOR Truth Table
Figure 7. The Exclusive-OR and Exclusive-NOR Functions
Some basic properties of the XOR and XNOR functions are listed in Table 8.
Table 8. Properties of the XOR and XNOR Functions
x :+: 0 = x x :: 0 = /x x :+ 1 = /x x :: 1 = x x :+: x = 0 x :: x = 0 x :+: /x = 1 x :: /x = 1 x :+: y = y :+: x x :: y = y :: x x :+: y = :+: z = (x :+: y) :+: z x :: y :: z = (x :: y) :: z) = x :+: (y :+: z) = x :: (y :: z) x :+: y = /x :+: /y x :: y = /x :: /y / (x :+: y) = /x :+: y / (x :: y) = /x :: y = x :+: /y = x :: /y = x :+: y = x :+: y x :+: y = x /y + /xy x :: y = x* y + /x/y x :+: x y = x/y x :: x* y = /x + y x :+: /xy = x + y x :: /xy = /x * /y x (y :+: z) = (xy) :+: (xz) x + (y :: z) = (x + y) :: (x + z) /x(y :+: z) = (x + y) :+: (x + z) /x + (y :: z) = (xy) :: (x*z)
XOR XNOR
When deriving equations from a Karnaugh map, XOR and XNOR functions can usually be identified by their characteristic pattern. Exactly what the operands are may or may not be obvious for more complicated func- tions. Some examples are shown in Figure 8.
The XOR gate can be used as an “UNLESS” operator. In other words, the function, A = X :+: Y can be interpreted as:
“A will have the same value as X UNLESS Y is true.”
This can be helpful when trying to derive a logic equation for a function which can be described in words.
6-12 Logic Reference Guide
90000A-
S
R
Q
Q
Q
S^ Q
R
Figure 10. An S-R Latch
Table 9. S-R Latch Truth Table S R Q+ 0 0 Q 0 1 0 1 0 1 1 0 Not allowed
The transfer function for this latch can be derived with a Karnaugh map, as shown in Figure 11. By choosing either 1’s or 0’s, we can obtain two representations:
a. Q+ = S+/RQ b. /Q+ = R+/S/Q
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Q S R
00
01
11
10
1
0 0
X X
1 1
0 1
Q+
0
Q S R
00
01
11
10
1
0 0
X X
1 1
0 1 0
/Q+ a. Q+ = S + /RQ b. /Q+ = R + /S/Q
Figure 11. Karnaugh Map for an S-R Latch
Waveforms illustrating the operation of the S-R latch are shown in Figure 12.
There are some applications where it is desirable for the input data to be effective only when another signal— usually called a control signal—is active. The circuit of Figure 10 can be modified to give an S-R latch with a control input, as shown in Figure 13. The operation of this circuit is summarized in Table 10 and Figure 14.
The S-R latch is somewhat restrictive, since both inputs cannot be HIGH at the same time. The other latch types are based on the S-R latch, but have additional logic which removes the input restrictions.
S
R
Q
90000A-
Figure 12. S-R Latch Behavior
S
C
R
S
R
Q
Q
Q
Q
S C R
Q
Q
90000A-
Figure 13. Adding a Control Input to an S-R Latch
Table 10. Truth Table for an S-R Latch with a Control Input S R C Q+ X X 0 Q 0 0 1 Q 0 1 1 0 1 0 1 1 1 1 1 Not allowed
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S
R
C
Q
90000A-
Figure 14. Behavior of an S-R Latch with a Control Input
D-Type Latches (Transparent Latches)
A single-input latch can be formed by adding some logic to the controlled S-R latch in Figure 13; this gives rise to the D-type latch in Figure 15. This latch is often called a transparent latch, since data on the input passes right through to the output as long as the control input is HlGH. If the control input is set LOW, then the latch holds whatever data was present when the control went LOW. With this type of latch, the control is usually called agate.
The behavior of the D-type latch is shown in Table 11 and Figure 16.
The basic transfer function for a D-type latch can be de- rived from the Karnaugh map in Figure 17.
G
Q
Q
D
G
Q
Q
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S
C
R
Q
Q
D
Figure 15. A D-Type (Transparent) Latch
Table 11. Truth Table for a D-Type Latch D G Q+ X 0 Q 0 1 0 1 1 1
D
G
Q
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Figure 16. D-Type (Transparent) Latch Behavior
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Q D G
00
01
11
10
1
0 0
1 1
0 1
0 1
Q+
0
Q D G
00
01
11
10
1
0 0
1 1
0 1
0 1 0
/Q+ a. Q+ = DG + D/G b. /Q+ = /DG + /Q/G**
Q+ = DG + Q/G /Q+ = /DG + /Q/G
Figure 17. Karnaugh Maps for a D-Type Latch
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J
K
Q
90000A-
δτ δτ
a. Falling Edge Race Conditions
Expected Levels
J
K
Q
δτ δτ
b. Rising Edge Race Conditions
Expected Levels
J
K
Q
tPD OF Latch^ c. Possible Oscillation
Figure 20. Hazards Inherent in a J-K Latch
6-16 Logic Reference Guide
90000A-
J Q K
00
01
11
10
1
0 0
1 0
1 1
0 1
Q+
0
J Q K
00
01
11
10
1
0 0
1 0
1 1
0 1 0
/Q+ a. Q+ = J/Q + /KQ b. /Q+ = /J/Q + KQ**
Figure 21. Karnaugh Maps for a J-K Latch
T-Type Latches T-type latches are formed by connecting the J and K in- puts of a J-K latch together to form a single input, as shown in Figure 22. This latch has two possible func- tions: hold the present state or invert the output, as summarized in Table 14. ‘T’ stands for ‘trigger’ or ‘toggle’ depending on who you talk to. That is, when T is HIGH, a change at the output is triggered; or, put an- other way, raising T causes the output to toggle.
J
K
Q
Q
Q
Q
T
Q
Q
90000A-
T
Figure 22. A T-Type Latch
Table 14. The Truth Table for a T-Type Latch T Q+ 0 Q 1 /Q
This Latch also has the problem that if T is left HIGH for too long, the output will oscillate. However, since there is only one input, the race condition problems of the J-K latch have been eliminated. Unfortunately, this comes at the cost of initialization. There is now no way to get the output into a fixed state without knowing what the previous state was. Thus, this device is not very useful without some kind of initialization circuit.
The general waveforms for a T-type latch are shown in Figure 23.
T
Q
tPD OF Latch (^) 90000A-
Figure 23. Behavior of a T-Type Latch
6-18 Logic Reference Guide
The simplicity of this flip-flop makes it the most widely used flip-flop. However, functions are sometimes more conveniently expressed using J-K flip-flops, or using T-type flip-flops. If we replace the D signal with the transfer function for one of the other flip-flop types, we can then emulate that flip-flop type in the D-type flip-flop. This is equivalent to taking a latch and placing a clocked D-type flip-flop after the latch output for synchronization. Figure 26 illustrates how each flip-flop can be emulated in a D-type flip-flop. The standard schematic symbols for the flip-flop types are also shown.
Table 15 summarizes the transfer functions for all of the flip-flop types. These functions can directly be used to emulate a particular flip-flop type in a D-type flip-flop. This can be particularly useful since D-type flip-flops are available in most registered PLDs.
S
R
Clock
Qp
Qn
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Figure 25. Behavior of a Clocked S-R Flip-Flop for Positive (Qp) and Negative (Qn) Edge-Triggered S-R Flip-Flops
Logic Reference Guide 6-
D Q
Q
Q
Q
J
K
Q
Q
90000A-
J
K
Q
Q
J
K
Clock
D Q
Q
a. Clocked D-Type Flip-Flop
D Q
Q
Q
Q
T Q
Q
T
Q
Q
T
Clock
b. Clocked J-K Flip-Flop
D Q
Q
Q
Q
S Q
T Q
Q
R Q
Clock
c. Clocked T-Type Flip-Flop
d. Clocked S-R Flip-Flop
S (^) S
R
Clock
Figure 26. Clocked Flip-Flops. All can be Emulated with a D-Type Flip-Flop
Logic Reference Guide 6-
Converting Between Bases
Base-2 <–> Base-
Converting a binary number to a decimal number is accomplished by using equation 1 directly.
Example:
Converting 110100.011 2 to decimal:
Y = 110100.
= 1 • 25 + 1• 24 + 0• 2 3 + 1• 2 2 + 0• 21 + 0• 20 + 0• 2 –1^ + 1 • 2 –2^ + 1• 2 – = 32 + 16 + 4 +.25 +. = 52.
When converting whole numbers from decimal to bi- nary, the decimal number is repeatedly divided by 2. Integer division is used, so the quotients are “rounded down” to the next integer. The remainders form the dig- its of the number. The least significant digit is the first one calculated.
Example:
Converting 61 10 to binary:
61/2 = 30 remainder = 1 LSB 30/2 = 15 remainder = 0 15/2 = 7 remainder = 1 7/2 = 3 remainder = 1 3/2 = 1 remainder = 1 1/2 = 0 remainder = 1 MSB
6110 =111101 2
When converting a decimal fraction into a binary frac- tion, the decimal number is multiplied by 2. This results in a whole number and a fraction. The whole number is a digit; the procedure is repeated on the new fraction. This procedure is repeated until the fractional portion is zero. If the procedure does not terminate, then the result is a repeating fraction. The first digit calculated is the most significant digit.
Example:
Converting .1625 10 to binary:
0.1625•2 = 0.3250 whole portion = 0 MSB 0.3250•2 = 0.65 whole portion = 0 0.65•2 = 1.3 whole portion = 1 0.3•2 = 0.6 whole portion = 0 0.6•2 = 1.2 whole portion = 1 0.2•2 = 0.4 whole portion = 0 0.4•2 = 0.8 whole portion = 0 0.8•2 = 1.6 whole portion = 1 0.6•2 = 1.2 whole portion = 1
Here we see that the fraction will repeat, since we have already multiplied 0.6 earlier. Thus
0.1625 10 = 0.00101001100110011... 2
For mixed numbers, it is necessary to calculate the whole and fractional portions separately. Thus, for ex- ample, we know that
61.1625 10 = 111101.0010100110011... 2
These are actually general procedures which can be used to convert a decimal number into any base, and vice versa.
Examples:
- Converting 321.54 8 to decimal:
Y = 3• 82 + 2• 81 +1• 80 + 5• 8 –1^ + 4• 8 – = 192 + 16 + 1 + .625 +. = 209. 321.54 8 = 209.6875 10
- Converting 106.10375 10 to octal:
106/8 = 13 remainder = 2 LSB 13/8 = 1 remainder = 5 1/8 = 0 remainder = 1 MSB
Thus, the whole portion is 151 8.
0.10375•8 = 0.83 whole portion = 0 MSB 0.83•8 = 6.64 whole portion = 6 0.64•8 = 5.12 whole portion = 5 0.12•8 = 0.96 whole portion = 0 0.96•8 = 7.68 whole portion = 7 0.68•8 = 5.44 whole portion = 5
At this point we have enough significant digits. We could continue either until the procedure terminated, or until the pattern started repeating. However, those last digits are not likely to be significant. Thus, we can approxi- mate by saying that...
106.10375 10 =152.065075 8
- Converting 31F.A2 16 to decimal:
Y = 31F.A2 16 = 3• 162 + 1• 161 + 15• 160 + 10• 16 –1^ +2• 16 – = 768 + 16 + 15 + 0.625 + 0. = 799. 31F.A2 16 = 799.6328125 10
- Converting 7689.100854 10 to hexadecimal:
7689/16 = 480 remainder = 9 LSB 480/16 = 30 remainder = 0 30/16 = 1 remainder = E 1/16 = 0 remainder = 1 MSB
6-22 Logic Reference Guide
Thus, the whole portion is 1EO9 16.
0.100854•16 = 1.613664 whole portion = 1 MSB 0.613664•16 = 9.818624 whole portion = 9 0.818624•16 = 13.097984 whole portion = D 0.097984•16 = 1.567744 whole portion = 1 0.567744•16 = 9.083904 whole portion = 9 0.083904•16 = 1.342464 whole portion = 1
Again, we likely have enough digits at this point. The ex- act fraction could be either very long or a long repeating pattern. For our purposes, we can approximate the overall result as:
7689.100854 10 = 1E09.19D191 16
Binary <–> Octal, Hexadecimal
Converting between the binary-related systems is very easy. The procedure consists of dividing the binary dig- its into groups, and replacing each group with an appropriate digit. For this reason, octal and hexadeci- mal numbers are often used to shorten long binary numbers.
To convert from binary to octal, group the digits by three, starting on each side of the binary point, and then con- vert each group of three digits into its corresponding octal digit. Leading and trailing zeroes may have to be added to the left of the whole portion and the right of the fractional portion, respectively, to make complete groups of three binary digits.
Example:
Converting 11011010110101.001001101 2 to octal:
Divide into groups of three digits:
Thus 11011010110101.001001101 2 = 33265.115 8
To convert from binary to hexadecimal, the digits are di- vided into groups of four digits, and then given their corresponding hexadecimal digits. Again, leading and/ or trailing zeroes may be needed.
Example:
Converting 100101011101100.110110001 2 to hexa- decimal:
Divide into groups of four digits:
4 A E C. D 8 8
Thus 100101011101100.110110001 2 = 4AEC.D88 16
To convert from octal or hexadecimal to binary, merely expand each digit into its corresponding binary representation.
Examples:
- Convert 7324.34 8 to binary:
Thus 7324.34 8 = 111011010100.0111 2
- Convert 1A2.3F5 16 to binary:
1 A 2. 3 F 5
Thus 1A2.3F5 16 = 110100010.001111110101 2
Binary Arithmetic
Positive binary arithmetic is very simple, and completely analogous to decimal arithmetic. However, if we are re- stricted to positive numbers, then we are also restricted to addition. We need a means of representing negative numbers. Using a dash ‘–’ is unacceptable for represen- tation in a computer. There are two general schemes which can be used. In binary systems, they are referred to as1s complement and2s complement representa- tion, although they can be generalized for any base system asdiminished-radix complement andradix com- plement representation.
One’s Complement Representation
The one’s complement of a binary number can be calcu- lated by inverting all of the bits of the number. Fractions are handled exactly the same way, although this is con- venient only for fixed-point arithmetic. Floating-point arithmetic requires other methods, which will not be dis- cussed here.
Example:
Finding the one’s complement of 110111.0101:
001000.1010 (Inverting each bit)
Thus, the one’s complement of 110111.0101 is 001000.1010.
The sign of a number is determined by the most signifi- cant bit. If the MSB is 0 the number is positive; if the MSB is 1, then the number is negative. Zero is represented by all bits being zero. However, one normally thinks of zero as being its own complement. But if we take the one’s complement of zero,
0000 1111
we see that 1111 is another representation of zero. Thus, in an eight-bit representation, positive numbers range from 00000001 to 01111111; negative numbers range from 10000000 to 11111110. Note that there are just as many negative numbers as positive numbers.
