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Chapter 3A: Digital Components: SSI and MSI Circuits
At this point, we have discussed the basic Boolean expressions and their implementation using the basic four digital gates: AND, OR, NOT, and XOR. We have mentioned several other gates, including the NAND and NOR gates, but not made much use of them. In this section, we shall discuss two topics associated with these gates.
- The implementation of these digital gates using actual TTL chips.
- MSI (Medium Scale Integration) chips that extend the functionality of these gates. Rather than describe the TTL (Transistor-Transistor Logic) chips in the abstract, we shall look at chips that implement our four basic functions. The first one will be described in a bit more detail, in order to touch on those inputs that are necessary for the actual electrical implementation, but which seem unnecessary when we view the gate in purely logical terms. NOT The basic not function is implemented in a DIP (Dual In-Line Pin) chip with the name 7404. All digital chips of interest to this course will be found in the 7400 series, having names such as 74LS04, indicating a “low signal” or low power variant of the chip. The smaller DIP chips have 14 pins. Of these 14, at least one pin must be used to power the chip and one used to connect it to ground, leaving 12 pins available for input and output. The basic NOT requires one input and one output; thus this chip is called a hex inverter and contains six NOT gates. The basic diagram of the chip is shown below. Figure: The SN74LS04 Hex Inverter Note that the pins are arrayed in two rows of seven each, thus the name DIP. The notch here shown on the left of the figure, is used to orient the chip and identify the pins, which otherwise bear no visible markings. To use one of these chips to implement the logical NOT function, one must first connect the power (pin 14) to the appropriate voltage (usually five volts), connect the ground appropriately, and then select one of the input pins and its associated output pin. Thus, one might have input to pin 5 and output from pin 6. Page 1 of 17 Chapter 3A Revised June 20, 2005
OR
The basic two-input OR gate is implemented with an SN74LS32 chip. As each 2-input OR gate has two inputs and one output, the 12 non-power related pins on the chip can support four of these logic gates. The chip is shown in the figure below. Figure: The SN74LS32 Quad 2-Input OR AND The basic two-input AND gate is implemented with an SN74LS08 chip. As each 2-input AND gate has two inputs and one output, the 12 non-power related pins on the chip can support four of these logic gages. The chip is shown in the figure below. Figure: The SN74LS08 Quad 2-Input AND XOR (Exclusive OR) The basic two-input XOR gate is implemented with an SN74LS86 chip, shown below. Figure: The SN74LS86 Quad 2-Input XOR Page 2 of 17 Chapter 3A Revised June 20, 2005
Binary Codes Revisited Both the decoder-related circuits (decoders and encoders) and the multiplexer-related circuits (multiplexers and demultiplexers) depend on binary codes for their functioning. Because this is the case, we review binary codes for unsigned integers. Common examples of these circuits are based on either two-bit or three-bit arithmetic. Two bits can encode four numbers, 0 through 3 in unsigned binary. Three bits can encode eight numbers, 0 through 7 in unsigned binary. In general, N bits can encode 2N^ different numbers, 0 through 2N^ – 1 in unsigned binary. Binary Decimal The two-bit codes are 00 0 01 1 10 2 11 3 The three-bit codes are 000 0 001 1 010 2 011 3 100 4 101 5 110 6 111 7 Decoders and Encoders We now consider an important class of commercial circuits – encoders and decoders. These perform the functions suggested by the corresponding decimal-binary conversions. In conversion of a decimal number to binary, we obtain the binary equivalent of the number. An encoder has a number of inputs, usually a power of two, and a set of outputs giving the binary code for the “number” of the input. Encoders Consider a classic 2N-to-N encoder. The inputs are labeled I 0 , I 1 , …, IK, where K = 2N^ – 1. The assumption is that only one of the inputs is active; in our way of thinking only one of the inputs is 1 and the rest are 0. Suppose input J is 1 and the rest are 0. The output of the circuit is the binary code for J. Suppose a 32-to-5 encoder with input 18 active. The output Z is the binary code 10010; Z 4 = 1, Z 3 = 0, Z 2 = 0, Z 1 = 1, and Z 0 = 0. Common encoders include 8-to-3, 16-to-4, and 32-to-5. One common exception to the rule of 2N-to-N is a 10-to-4 encoder, which is used because decimal numbers are so common. Note that three binary bits are not sufficient to encode ten numbers, so we must use four bits and not produce the outputs 1010, 1011, 1100, 1101, 1110, or 1111. Page 4 of 17 Chapter 3A Revised June 20, 2005
We now present a detailed discussion and a design of a 10-to-4 encoder. We begin with a diagram that might illustrate a possible use of an encoder. In this example, the key pad has ten keys, one for each digit. When a key is pressed, the output line corresponding to that key goes to logic 1 (5 volts) and the other output lines stay at logic 0 (0 volts). Note that there are ten output lines from the key pad, one for each of the keys. These ten output lines form ten input lines into the 10-to-4 encoder. The 10-to-4 encoder outputs a binary code indicating which of the keys has been pressed. In a complete design, we would require some way to indicate that no key has been pressed. For our discussion, it is sufficient to ignore this common case and assume that a key is active. We first ask why we need four bits for the encoder. N bits will encode 2N^ different inputs. As a result, to encode M different items, we need N bits with 2N–1^ < M 2 N. To encode 10 inputs, we note that 2^3 < 10 24 , so we need 4 bits to encode 10 items. We now present a table indicating the output of the encoder for each input. In this example, we assume that at any time exactly one input is active. In the table at left, we label the inputs X 0 through X 9 , inclusive. To produce the equations for the outputs, we reason as follows. Y 3 is 1 when either X 8 = 1 or X 9 = 1. Y 2 is 1 when X 4 = 1 or X 5 = 1 or X 6 = 1 or X 7 = 1. Y 1 is 1 when X 2 = 1, X 3 = 1, X 6 = 1, or X 7 = 1. Y 0 is 1 when X 1 = 1, X 3 = 1, X 5 = 1, X 7 = 1, or X 9 = 1. Page 5 of 17 Chapter 3A Revised June 20, 2005 Input Y 3 Y 2 Y 1 Y 0 X 0 0 0 0 0 X 1 0 0 0 1 X 2 0 0 1 0 X 3 0 0 1 1 X 4 0 1 0 0 X 5 0 1 0 1 X 6 0 1 1 0 X 7 0 1 1 1 X 8 1 0 0 0 X 9 1 0 0 1
Again, the main exception to the N-to-2N^ rule for decoders is the 4-to-10 decoder, which is a common circuit. Note that it takes 4 bits to encode 10 items, as 3 bits will encode only 8. This author’s preference would be to use a 4-to-16 decoder and ignore some of the outputs, but this author does not establish commercial practice. Besides the 4-to-10 decoder chip would have fewer pins than a 4-to-16 chip, which requires at least 22 pins. Another issue is whether the signals are active high or active low. Our examples have been constructed for active high circuits. Consider the 4-to-16 decoder as an example. If the input code is 1001, then the output Z 9 is a logic 1 or +5 volts and all other outputs are logic 0 or 0 volts. This approach is active high. In real commercial circuits, we often have outputs as active low, in which case the above decoder would have output Z 9 as a logic 0 or 0 volts and all other inputs as logic 1 or +5 volts. This reflects an issue with design using real TTL circuits. We shall discuss this more when needed. Decoders have N inputs and 2N^ outputs. We consider a 2-to-4 decoder; thus N = 2. The design that we present will assume that the decoder is active high; again that the selected output becomes logic 1 (5 volts) and the others remain at logic 0 (ground or 0 volts). The decoder is based on the association of binary numbers to decimal numbers, as is shown in the figure at right. Since this is a 2-to-4 decoder, we have two inputs, labeled X 1 , and X 0 ; and four outputs, labeled Y 3 , Y 2 , Y 1 , and Y 0. The table below illustrates the functioning of a simple 2-to-4 decoder with outputs that are active high. X 1 X 0 Y 0 Y 1 Y 2 Y 3 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 0 1 0 1 1 0 0 0 1 The observation that leads to the design of the decoder is the obvious one that the values of X 1 , and X 0 determine the output selected. It does have the problem that one output is always selected. The way to cause all outputs to be deselected is to use an enable input. The Enable Input We now consider another important input to the decoder chip. This is the enable input. If the decoder enable signal is active high, then the decoder is active when enable is 1 and not active when enable = 0. We shall consider enabled-high decoders here. The enable input allows the decoder to be either enabled or disabled. For an active high decoder that is enabled high (Enable = 1 activates it) we have the following. Enable = 0 All outputs of the decoder are 0 Enable = 1 The selected output of the decoder is 1, all other outputs are 0. Page 7 of 17 Chapter 3A Revised June 20, 2005
One way to express the effect of the enable input is to use a modified truth table. Enable X 1 X 0 Y 0 Y 1 Y 2 Y 3 0 d d 0 0 0 0 1 0 0 1 0 0 0 1 0 1 0 1 0 0 1 1 0 0 0 1 0 1 1 1 0 0 0 1 Thus, all outputs are 0 when the enable input is 0. This is true without regard to the inputs. When the enable input is 1, the outputs correspond to the inputs. Here is a circuit diagram for a 2-to-4 decoder that is enabled high and active high. Note that the Enable input is passed as an input to all four of the AND gates used to produce the output of the decoder. As a result, when Enable = 0, all of the outputs are 0; the decoder is not active. When Enable = 1 in the above circuit, the other two inputs X 1 and X 0 will determine the one of the four outputs is set to 1; the others remaining 0. This is exactly how the active-high decoder should function. We now consider the use of decoders as elements in a circuit. Our discussions have focused on decoders that are active high with positive logic. For such encoders, the design calls for use with OR gates to implement a function expressed in canonical SOP form. Page 8 of 17 Chapter 3A Revised June 20, 2005
As examples, we show above the diagrams for both a four-to-on multiplexer (MUX) and a four-to-one demultiplexer (DEMUX). Note that each of the circuits has two control signals. For a multiplexer, the N control signals select which of the 2N^ inputs will be passed to the output. For a demultiplexer, the N control signals select which of the 2N^ outputs will be connected to the input. Multiplexers The output for a multiplexer can be represented as a Boolean function of the inputs and the control signals. As an example, we consider a 4-input multiplexer, with control signals labeled C 0 and C 1 and inputs labeled I 0 , I 1 , I 2 , and I 3. The output can be described as a truth table or algebraically. Note that each of the truth tables and algebraic expression shows the input that is passed to the output. The truth table is an abbreviated form of the full version, which as a table for independent variables C 0 , C 1 , I 0 , I 1 , I 2 , and I 3 would have 64 rows. C 1 C 0 M 0 0 I 0 0 1 I 1 M = C 1 ’C 0 ’I 0 + C 1 ’C 0 I 1 + C 1 C 0 ’I 2 + C 1 C 0 I 3 1 0 I 2 1 1 I 3 Multiplexers are generally described as 2N-to-1 devices. These multiplexers have 2N^ inputs, one of which is connected to the single output line. The N control lines determine which of the inputs is connected to the output. Here is a circuit for a 4-to-1 multiplexer. Note that the inputs are labeled X 3 , X 2 , X 1 , and X 0 here and I 3 , I 2 , I 1 , and I 0 in the multiplexer equation. Page 10 of 17 Chapter 3A Revised June 20, 2005
Demultiplexer Demultiplexers are generally described as 1-to-2N^ devices. These multiplexers have one input, which is connected to one of the 2N^ output lines. The N control lines determine which of the output line is connected to the input. Here is a circuit for a 1-to-4 demultiplexer. Note that, for good measure, we have added an enable-high to the demultiplexer. When this enable is 0, all outputs are 0. When this enable is 1, the selected output gets the input, X. Remember, that X can have a value of either 0 or 1. There is an equivalence between decoders and demultiplexers that many students notice. Consider an active-high 1-to-2N^ demultiplexer with N control signals, under the assumption that the selected output copies the input and the other outputs are set to logic 0. We then set the input to logic 1 and note that the output selected by the control signals is logic 1 while the other outputs are logic 0. We have converted the demultiplexer into an active high decoder. The following figure shows a 1-to-4 demultiplexer used as a 2-to-4 decoder. Note that the input to the circuit acting as a decoder is labeled X 1 and X 0. This input is placed into the control inputs of the demultiplexer, indicating which output should receive the input, set to the decoder enable signal. When Enable = 0, all of the outputs are 0, as required for the decoder. When Enable = 1, the X 1 X 0 input selects which output becomes 1 while the other outputs remain at
- This makes the DEMUX so configured to be functionally equivalent to a 2-to-4 decoder. Page 11 of 17 Chapter 3A Revised June 20, 2005
As an aside, we mention a common variant of the above circuit related to the “fan-out” problem. The fan-out of a circuit element is the number of gates receiving input. We assume that there is a circuit element providing input to each of the A, B, and C inputs. Consider the input line marked A. This input must drive five gates: the NOT gate producing A , and the AND gates producing the output^ AB^ C, ABC, AC, and AB. The following circuit is a variant of the above in which each of the A, B, and C inputs is providing input to only one gate – the first NOT gate of a double inverter. Such a step simplifies the use of a full adder in a digital design in that the user of the full adder does not need to worry about the load that the chip will place on the entire circuit. Page 13 of 17 Chapter 3A Revised June 20, 2005
More on Full Adders There are a number of ways to consider a full-adder. In our definition of the moment, a full- adder adds two single-bit numbers A and B, with a single-bit carry-in C to form a single bit sum and a single bit carry out. We repeat the Boolean formulae for these two functions. Schematically, we represent this in circuits as a box labeled FA, for Full-Adder. Note that there are two carry bits associated with a full-adder. When we need to distinguish them, we apply the labels Cin – for the Carry In, here labeled “C” Cout – for the Carry Out, here labeled “Carry” Single-bit adders are of no more use than a procedure in arithmetic for adding single digits. To make multiple bit adders, we follow the same practice as in decimal arithmetic, we form a way to add single digits and allow for both carry in and carry out. For example, we show a four-bit full adder. This adds two four bit numbers, A 3 A 2 A 1 A 0 and B 3 B 2 B 1 B 0. Note that the carry out of one stage becomes the carry in of the next higher stage, in the same manner as is done in decimal arithmetic when the carry out of the units becomes the carry in of the tens, the carry out of the tens becomes the carry in to the hundreds, etc. The circuit below shows the four-bit full-adder. Notice that the carry in to full-adder 0 has been grounded, thus forcing the carry in to that stage to be 0, as required. A sixteen-bit adder would be constructed by chaining together sixteen full-adders in the manner shown above. What we have described is called a ripple-carry adder , easy to construct but far too slow for commercial use. Nevertheless, it is an accurate model of a multi-bit adder and that is what we shall study. Page 14 of 17 Chapter 3A Revised June 20, 2005
For each number, bit 15 is the sign bit, bit 14 is the bit for 2^14 = 16384, bit 13 is the bit for 213 = 8192, etc. Conceptually, a 16-bit adder comprises sixteen one-bit full adders, each taking in a carry bit from the lower order adder and producing both a sum bit and a carry-out bit. The following figure shows the three high order full adders for the three high order bits. Overflow occurs in two cases When A 15 = 0, B 15 = 0, and S 15 = 1 Two positive numbers sum to a negative number When A 15 = 1, B 15 = 1, and S 15 = 0 Two negative numbers sum to a positive number To understand overflow, we need only to consider the full-adder used to add the two sign bits; in this case we consider the full adder for bit 15. It is easy to prove that overflow is not possible when adding numbers of opposite signs. When adding two valid 16 bit numbers, overflow can occur only when the magnitude of the sum is greater than the magnitude of either of the two input numbers – this can occur only when the two numbers have the same sign. Consider the two rows A 15 = 0, B 15 = 0, C 15 = 1, S 15 = 1 and A 15 = 1, B 15 = 1, C 15 = 0, S 15 = 0. These are the only two cases in which overflow occurs. Closer inspection of this full-adder table gives rise to a simpler method for identifying the overflow cases. Only in these two cases of overflow is C 16 C 15. For all other cases we have C 16 = C 15. So, our overflow detector is a circuit that detects when C 16 C 15. The Exclusive OR gate is exactly what we need; C 16 C 15 = 1 if and only if C 16 C 15. Thus, the signal is generated by Overflow = C 16 C 15 , or Overflow = C 32 C 31 for 32 bit numbers. Page 16 of 17 Chapter 3A Revised June 20, 2005 A 15 B 15 C 15 S 15 C 16 Overflow 0 0 0 0 0 No 0 0 1 1 0 YES 0 1 0 1 0 Not possible 0 1 1 0 1 Not possible 1 0 0 1 0 Not possible 1 0 1 0 1 Not possible 1 1 0 0 1 YES 1 1 1 1 1 No
Saturation Arithmetic We close this section with a discussion of a type of integer arithmetic in which overflow cannot occur. We consider 8-bit integers in both unsigned and two’s-complement form. The range of integers representable in 8-bits is as follows: Unsigned integers 0 to 255 Two’s-Complement – 128 to 127 Saturation arithmetic is most commonly used in computer graphics, where color values may be conveniently represented as a RGB triple of 8-bit integers, one integer for each of the Red, Green, and Blue intensities of the color. In such a situation, we want the addition operator to saturate at its maximum value rather than overflow. This avoids some rather bizarre visual effects in the graphics display, such as the appearance of black spots in a white region. The rule for saturation arithmetic is quite simple. If the value computed is not in the range representable for the data type, adjust it to the range by either setting it to the minimum or maximum value as appropriate. Consider saturated 8-bit unsigned arithmetic. All results must be in the range [0, 255], that is
- at least 0 and not greater than 255. 128 + 64 = 192 as in standard arithmetic 128 + 128 = 255 in standard arithmetic this overflows as 256 > 255. in saturation arithmetic this saturates at 255. 32 – 16 = 16 as in standard arithmetic 32 – 48 = 0 in standard arithmetic this causes an error. The following table summarizes the difference between standard and saturation arithmetic. Type of Arithmetic Result Greater Result Smaller Than Maximum Than Minimum Number Representable Number Representable Standard Arithmetic Error Error Saturation Arithmetic Set the result Set the result to the maximum to the minimum number representable number representable Page 17 of 17 Chapter 3A Revised June 20, 2005
