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Digital Circuitry - Digital Circuits and Systems - Lecture Notes, Study notes of Computer Science

These are the Lecture Notes of Digital Circuits and Systems which includes Present State, Principle, Memory Elements, Elementscombinational Logic, Description, Circuit and Create, Number of States, Binary Codes, Letter Symbol etc. Key important points are: Digital Circuitry, Programmable Logic Devices, Implement, Discrete Gates, Logic Functions, Difficult to Minimise, Single Device, Expensive, Performance, Custom Logic

Typology: Study notes

2012/2013

Uploaded on 03/22/2013

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Section 6 – Memory
Programmable Logic Devices
Can implement logic by a number of methods:
SSI (Discrete Gates) Need lots of ICs
MSI (Logic Functions) needs fewer ICs but still
difficult to minimise
PLDs Single device usually.
o More reliable, difficult to copy
Gate Array More expensive than PLDs but higher
performance and more options
o More flexible
ASIC (Application Specific IC)
o Standard Cells higher initial costs
o Custom Logic highest initial costs
o ASIC requires high volume to make worthwhile
o Long turnaround
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Section 6 – Memory

Programmable Logic Devices

Can implement logic by a number of methods:

• SSI (Discrete Gates) – Need lots of ICs

• MSI (Logic Functions) – needs fewer ICs but still

difficult to minimise

• PLDs – Single device usually.

o More reliable, difficult to copy

• Gate Array – More expensive than PLDs but higher

performance and more options

o More flexible

• ASIC (Application Specific IC)

o Standard Cells – higher initial costs

o Custom Logic – highest initial costs

o ASIC requires high volume to make worthwhile

o Long turnaround

PROM

Programmable OR array

Fixed

AND

array

A
A
A
A
A

Blow fuses on all non required connections

PLA – Programmable AND and OR arrays

Only subset of possible AND terms provided. Each AND gate has

connections to each i/p. By leaving appropriate fuse intact, any i/p or its

complement can be present in any AND term.

PLA Eg

Unwanted connections are "blown"

Equations

Programming

1 = asserted in term

0 = negated in term

- = does not participate

1 = term connected to output

0 = no connection to output

Input Side:

Output Side:

F0 = A + B' C'

F1 = A C' + A B

F2 = B' C' + A B

F3 = B' C + A

Another PLA Example: Magnitude Comparator

PAL has programmable AND-array, but fixed OR-array.

A given column of the OR array has access to only a subset of the possible product terms

PALs simpler to understand and use than PLAs and have performance

advantages: a fuse array has high capacitance which causes delay.

Reducing no. of AND terms reduces cost and power consumption.

First PALs suffered from restrictions of fixed i/p and o/p nos. And fixed o/p

polarity.

PROM

Not unlike a PLA

structure with a

fully decoded

AND array!

ROM vs. PLA:

ROM approach advantageous when

(1) design time is short (no need to minimize output functions)

(2) most input combinations are needed (e.g., code converters)

(3) little sharing of product terms among output functions

ROM problem: size doubles for each additional input, can't use don't cares

PLA approach advantangeous when

(1) design tool like espresso is available

(2) there are relatively few unique minterm combinations

(3) many minterms are shared among the output functions

PAL problem: constrained fan-ins on OR planes

Memory array
2 n^ words by
m bits
m output
lines
n address
lines
Decoder
2 n^ word
lines

Registered (Sequential) PAL:

16R4 PAL:

22v10 o/p macrocell

Complex PLD

X3000 series Configurable Logic Block

FPGA Design: