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DC Analysis of BJT Circuits - Lecture Slides | EE 334, Study notes of Electrical and Electronics Engineering

University of South Alabama (USA)Electrical and Electronics Engineering
Prof. Aurangzeb Khan

Material Type: Notes; Professor: Khan; Class: Analog and Digital Electronics; Subject: Electrical Engineering; University: University of South Alabama; Term: Fall 2008;

Typology: Study notes

Pre 2010

Uploaded on 08/18/2009

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EE 334
Analog and Digital
Electroznics
Bipolar Junction Transistor
(BJT)
DC-Analysis of BJT Circuits
DC Equivalent Circuit for npn Common Emitter
DC-Analysis of Common Emitter
Circuit
B
BEBB
BR
)on(VV
I−
=
BC II
β
=
CCCCCE RIVV −=
CECCECBEBT VIVI)on(VIP ≅+=
Problem 5.8
•The pnp transistor shown in Fig. has
a common base current gain
α
=
0.992. Determine the emitter current
such that VC= -1.2 V
pf3
pf4
pf5

Partial preview of the text

Download DC Analysis of BJT Circuits - Lecture Slides | EE 334 and more Study notes Electrical and Electronics Engineering in PDF only on Docsity!

EE 334

Analog and Digital

Electroznics

Bipolar Junction Transistor

( BJT

DC-Analysis of

BJT

Circuits

DC Equivalent Circuit for

npn^ Common Emitter

DC-Analysis of Common Emitter

Circuit BE^ B BB B

R

)on(

V

V

I^

B C^

I

I

CC CC CE^

RI

V

V^

CEC CEC BEB T^

VI

VI

)on

(V

I

P^

Problem 5.

  • The

pnp^

transistor shown in Fig. has a common base current gain

α^ =

0.992. Determine the emitter currentsuch that

V= -1.2 VC^

Problem 5.

  • For the givencircuit,

β^ =

50,V

= 0.7 VBE

V= VB^

.C

Determine

V, IB^

E^

I^ C + V^ BE - I^ E

Load Line Model

Base-Emitter circuit relationships

BE^ B BB B B

V R VI −= R When

I= 0,B^

V^ BE

=^ V^ BB

When

V^ = BE^

^0 ,^ IB^ = V^ BB

/R^ B

Load Line Model

Collector-Emitter circuit relationships

CE^ C CC C C

V R VI −= R When

I= 0,C^

V^ CE

= V^ CC

When

V^ = CE^

^0 ,^ IC^ = V^ CC /R^ C

Q-point = Quiescent point

Collector-Emitter relationships • As^ I increases or decreases B^ –^ Q-point moves up or down theload line • If^ I increase too much B^ –^ Q-point pushed into saturationregion • If^ I<^ β^ Ic^

B – Then Saturation – Nonlinear relationship – V typically 0.1 to 0.3 V, CE(Sat)^ assume 0.2 V

-^ If^ VBB

< V(on) BE – I = 0,^ I^ B^ C^ = 0,^ I = 0 E^

-^ Cutoff mode

BJT Operation Applications •^ Generally analog circuits^ – Operate in forward active mode– Otherwise, very non-linear operation•^ Generally digital circuits^ – Operate between cut-off and saturationregions

Summary of Current-Voltage Relationships

in the Active Region

TEB

TBE

TEB

TBE

TEB

TBE

V/v S F FF C V/v S F FF CB

V/v S FE FC V/v S FE FC

V/v S E

V/v S E

eI i eI ii

eI i i eI i i

eI i

eI i

α^ ββ

α ββ

α α

α α

=

==

=

=

=

=

pnp

npn

(^

F^ F F F F F

FE F CB F EBF C

1

1

i i^1 i (^1) i i i

α^ α β β β α

β β β β

=−

=+

 =+ += =

s transistorboth For

Problem-Solving Technique:

Bipolar DC Analysis

1. Assume

that the transistor is biased in forward active mode a.^ V^ BE

=^ V^ BE

(on)I^ ,^ B

0, & I

=^ βIC^

B

  1. Analyze ‘

linear

’ circuit

  1. Evaluate the resulting state of transistora. If

V^ > CE^ V^ (sat)CE

,^ assumption is correct

b. If^ I

< 0 , transistor likelyB^

in cutoff

c.^ If^ V^ < 0 CE^

, transistor likely in

saturation

  1. If initial assumption is

incorrect

,^ make

new assumption and return to Step 2

Example 5.

  • For the circuit shown in Fig., thetransistor parameters are

β^ = 100

and^

V(on)BE^

= 0.7 V, and

V(sat)CE^

0.2 V. Calculate the voltages and thecurrents in the transistor circuit.

Design Ex 5.

  • Design the circuitshown in Fig. suchthat

I^ CQ^

= 1.5 mA and^

V= 4 V,c^ assume

β^ = 100.

I^ CQ^ + V^ - BE I^ E

Example (TYU 5.11) For the circuit shown in Fig. Find

I^ ,E^

I^ , I^ B^ C

,^ and

VCE^

if^ β^ = 75.^ I^ B

I^ C