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Data Dependence Distances - Computer Architecture - Lecture Slides, Slides of Computer Architecture and Organization

Data Dependence Distances, SRC hazard correction, Data forwarding, RTL for data forwarding, Pipelining, Instruction Level Parallelism, Superscalar Architecture are the topics professor discuss in class.

Typology: Slides

2011/2012

Uploaded on 11/03/2012

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Data Dependence Distances
The following table shows instruction pair hazard interaction
Instruction
class alu load ladr brl
6/4 6/5 6/4 6/2
alu 2/3 4/1 4/2 4/1 4/1
load 2/3 4/1 4/2 4/1 4/1
ladr 2/3 4/1 4/2 4/1 4/1
store(rb) 2/3 4/1 4/2 4/1 4/1
store(ra) 2/4 4/1 4/1 4/1 4/1
branch 2/2 4/2 4/3 4/2 4/1
Write to register file
Data Available Normal/Earliest stage
Read from register file
Data Available Normal/Earliest stage
Normal/forwarded
No hazard
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pf3
pf4
pf5
pf8

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1

Data Dependence Distances

The following table shows instruction pair hazard interaction

Instruction class

alu load ladr brl

alu 2/3 4/1 4/2 4/1 4/ load 2/3 4/1 4/2 4/1 4/ ladr 2/3 4/1 4/2 4/1 4/ store(rb) 2/3 4/1 4/2 4/1 4/ store(ra) 2/4 4/1 4/1 4/1 4/ branch 2/2 4/2 4/3 4/2 4/

Write to register file Data Available Normal/Earliest stage

Read from register file

Data Available Normal/Earliest stage

Normal/forwarded

No hazard

2

SRC hazard correction:data forwarding

  • The hazard detection is required

between stage 3-4, and between

stage 3-

  • The testing and forwarding circuit

employ wider IRs to store the data

required in later stages

4

RTL for data forwarding

dependence RTL

Stage 3-5 alu5&alu3:((ra5=rb3):X←Z5,

(ra5=rc3)&!imm3: Y ← Z5);

Stage 3-4 alu4&alu3:((ra4=rb3):X←Z4,

(ra4=rc3)&!imm3: Y ← Z4);

Data forwarding

Hazard detection

5

Data

forwarding

hardware

Instruction Fetch

Decode and Operand Read

ALU Operation

Memory Access

Register Writeback

X3 Y

Z

Z

IR

IR

IR

PC

MD

MD

IR5 (^) Hazard Det/forward unit

Hazard Det/forward unit

ALU

Mp7 MUX^ MUX^ Mp

7

Instruction-Level

Parallelism

• Superscalar Architecture

issues multiple instruction

simultaneously

• VLIW Architecture

based on a very long instruction

word.

8

Superscalar Architecture

• It has one or more IUs (integer units) ,

FPUs (floating point units), BPUs

(branch prediction units)

• It divides instructions into three

classes

 Integer  Floating point  Branch prediction