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and Disabling Interrupts, Handling Multiple Devices, Controlling Device Requests, Exceptions, Use Of Interrupts in Operating Systems, Pentium Interrupt Structure, Direct Memory Access, Busses, Interface Circuits, Standard I/O
ACCESSING I/O DEVICES
A simple arrangement to connect I/O devices to a computer is to use a single bus structure. It consists of three sets of lines to carry Address Data Control Signals. When the processor places a particular address on address lines, the devices that recognize this address responds to the command issued on the control lines.
The processor request either a read or write operation and the requested data are transferred over the data lines.
When I/O devices & memory share the same address space, the arrangement is called memory mapped I/O.
Fig 3.1A single-bus structure
Eg:- Move DATAIN, Ro Reads the data from DATAIN then into processor register Ro. Move Ro, DATAOUT Send the contents of register Ro to location DATAOUT. DATAIN Input buffer associated with keyboard. DATAOUT Output data buffer of a display unit / printer.
Fig: I/O Interface for an Input Device
and Disabling Interrupts, Handling Multiple Devices, Controlling Device Requests, Exceptions, Use Of Interrupts in Operating Systems, Pentium Interrupt Structure, Direct Memory Access, Busses, Interface Circuits, Standard I/O
Address Decoder: It enables the device to recognize its address when the address appears on address lines.
Data register It holds the data being transferred to or from the processor. Status register It contains infn/. Relevant to the operation of the I/O devices.
The address decoder, data & status registers and the control circuitry required to co-ordinate I/O transfers constitute the device’s I/F circuit. For an input device, SIN status flag in used SIN = 1, when a character is entered at the keyboard. For an output device, SOUT status flag is used SIN = 0, once the char is read by processor.
DIR Q Interrupt Request for display. KIR Q Interrupt Request for keyboard. KEN keyboard enable. DEN Display Enable. SIN, SOUT status flags.
The data from the keyboard are made available in the DATAIN register & the data sent to the display are stored in DATAOUT register
and Disabling Interrupts, Handling Multiple Devices, Controlling Device Requests, Exceptions, Use Of Interrupts in Operating Systems, Pentium Interrupt Structure, Direct Memory Access, Busses, Interface Circuits, Standard I/O
Fig:Transfer of control through the use of interrupts
The processor first completes the execution of instruction i Then it loads the PC(Program Counter) with the address of the first instruction of the ISR. After the execution of ISR, the processor has to come back to instruction i + 1. Therefore, when an interrupt occurs, the current contents of PC which point to i +1 is put in temporary storage in a known location. A return from interrupt instruction at the end of ISR reloads the PC from that temporary storage location, causing the execution to resume at instruction i+1. When the processor is handling the interrupts, it must inform the device that its request has been recognized so that it remove its interrupt requests signal. This may be accomplished by a special control signal called the interrupt acknowledge signal. The task of saving and restoring the information can be done automatically by the processor. The processor saves only the contents of program counter & status register (ie) it saves only the minimal amount of information to maintain the integrity of the program execution. Saving registers also increases the delay between the time an interrupt request is received and the start of the execution of the ISR. This delay is called the Interrupt Latency. Generally, the long interrupt latency in unacceptable. The concept of interrupts is used in Operating System and in Control Applications, where processing of certain routines must be accurately timed relative to external events. This application is also called as real-time processing.
and Disabling Interrupts, Handling Multiple Devices, Controlling Device Requests, Exceptions, Use Of Interrupts in Operating Systems, Pentium Interrupt Structure, Direct Memory Access, Busses, Interface Circuits, Standard I/O
Interrupt Hardware:
Fig:An equivalent circuit for an open drain bus used to implement a common interrupt request line
A single interrupt request line may be used to serve „n‟ devices. All devices are connected to the line via switches to ground. To request an interrupt, a device closes its associated switch, the voltage on INTR line drops to 0(zero). If all the interrupt request signals (INTR1 to INTRn) are inactive, all switches are open and the voltage on INTR line is equal to Vdd. When a device requests an interrupts, the value of INTR is the logical OR of the requests from individual devices.
(ie) INTR = INTR1+…………+INTRn
INTR It is used to name the INTR signal on common line it is active in the low voltage state. Open collector (bipolar ckt) or Open drain (MOS circuits) is used to drive INTR line. The Output of the Open collector (or) Open drain control is equal to a switch to the ground that is open when gates input is in „0‟ state and closed when the gates input is in „1‟ state. Resistor „R‟ is called a pull-up resistor because it pulls the line voltage upto the high voltage state when the switches are open.
ENABLING AND DISABLING INTERRUPTS
The arrival of an interrupt request from an external device causes the processor to suspend the execution of one program & start the execution of another because the interrupt may alter the sequence of events to be executed. INTR is active during the execution of Interrupt Service Routine. There are 3 mechanisms to solve the problem of infinite loop which occurs due to successive interruptions of active INTR signals.
and Disabling Interrupts, Handling Multiple Devices, Controlling Device Requests, Exceptions, Use Of Interrupts in Operating Systems, Pentium Interrupt Structure, Direct Memory Access, Busses, Interface Circuits, Standard I/O
The code supplied by the processor indicates the starting address of the ISR for the device. The code length ranges from 4 to 8 bits. The location pointed to by the interrupting device is used to store the staring address to ISR. The processor reads this address, called the interrupt vector & loads into PC. The interrupt vector also includes a new value for the Processor Status Register. When the processor is ready to receive the interrupt vector code, it activate the interrupt acknowledge (INTA) line.
Interrupt Nesting: Multiple Priority Scheme:
In multiple level priority scheme, we assign a priority level to the processor that can be changed under program control. The priority level of the processor is the priority of the program that is currently being executed. The processor accepts interrupts only from devices that have priorities higher than its own. At the time the execution of an ISR for some device is started, the priority of the processor is raised to that of the device. The action disables interrupts from devices at the same level of priority or lower.
Privileged Instruction:
The processor priority is usually encoded in a few bits of the Processor Status word. It can also be changed by program instruction & then it is write into PS. These instructions are called privileged instruction. This can be executed only when the processor is in supervisor mode. The processor is in supervisor mode only when executing OS routines. It switches to the user mode before beginning to execute application program.
Privileged Exception:
User program cannot accidently or intentionally change the priority of the processor & disrupts the system operation. An attempt to execute a privileged instruction while in user mode, leads to a special type of interrupt called the privileged exception.
Fig: Implementation of Interrupt Priority using individual Interrupt request acknowledge lines
and Disabling Interrupts, Handling Multiple Devices, Controlling Device Requests, Exceptions, Use Of Interrupts in Operating Systems, Pentium Interrupt Structure, Direct Memory Access, Busses, Interface Circuits, Standard I/O
Each of the interrupt request line is assigned a different priority level. Interrupt request received over these lines are sent to a priority arbitration circuit in the processor. A request is accepted only if it has a higher priority level than that currently assigned to the processor,
Simultaneous Requests: Daisy Chain: The interrupt request line INTR is common to all devices. The interrupt acknowledge line INTA is connected in a daisy chain fashion such that INTA signal propagates serially through the devices. When several devices raise an interrupt request, the INTR is activated & the processor responds by setting INTA line to 1. this signal is received by device.
and Disabling Interrupts, Handling Multiple Devices, Controlling Device Requests, Exceptions, Use Of Interrupts in Operating Systems, Pentium Interrupt Structure, Direct Memory Access, Busses, Interface Circuits, Standard I/O
Kinds of exception: Recovery from errors Debugging Privileged Exception
Recovery From Errors:
Computers have error-checking code in Main Memory , which allows detection of errors in the stored data. If an error occurs, the control hardware detects it informs the processor by raising an interrupt. The processor also interrupts the program, if it detects an error or an unusual condition while executing the instance (ie) it suspends the program being executed and starts an execution service routine. This routine takes appropriate action to recover from the error.
Debugging:
System software has a program called debugger, which helps to find errors in a program. The debugger uses exceptions to provide two important facilities
They are Trace Breakpoint
Trace Mode: When processor is in trace mode , an exception occurs after execution of every instance using the debugging program as the exception service routine. The debugging program examine the contents of registers, memory location etc. On return from the debugging program the next instance in the program being debugged is executed The trace exception is disabled during the execution of the debugging program.
Break point:
Here the program being debugged is interrupted only at specific points selected by the user. An instance called the Trap (or) software interrupt is usually provided for this purpose. While debugging the user may interrupt the program execution after instance „I‟ When the program is executed and reaches that point it examine the memory and register contents.
Privileged Exception:
To protect the OS of a computer from being corrupted by user program certain instance can be executed only when the processor is in supervisor mode. These are called privileged exceptions.
and Disabling Interrupts, Handling Multiple Devices, Controlling Device Requests, Exceptions, Use Of Interrupts in Operating Systems, Pentium Interrupt Structure, Direct Memory Access, Busses, Interface Circuits, Standard I/O
When the processor is in user mode, it will not execute instance (ie) when the processor is in supervisor mode , it will execute instance.
DIRECT MEMORY ACCESS
Explain the advantages of Direct Memory Access and its implementation in a
computer.( 11 Marks April 2015,April 2014,Dec 2014,Nov 2012 )
A special control unit may be provided to allow the transfer of large block of data at high speed directly between the external device and main memory , without continous intervention by the processor. This approach is called DMA. DMA transfers are performed by a control circuit called the DMA Controller.
To initiate the transfer of a block of words , the processor sends,
Starting address Number of words in the block Direction of transfer.
When a block of data is transferred , the DMA controller increment the memory address for successive words and keep track of number of words and it also informs the processor by raising an interrupt signal. While DMA control is taking place, the program requested the transfer cannot continue and the processor can be used to execute another program. After DMA transfer is completed, the processor returns to the program that requested the transfer.
Fig:Registes in a DMA Interface
R/W Determines the direction of transfer. When R/W =1 , DMA controller read data from memory to I/O device. R/W =0 , DMA controller perform write operation. Done Flag=1 , the controller has completed transferring a block of data and is ready to receive another command. IE=1 , it causes the controller to raise an interrupt (interrupt Enabled) after it has completed transferring the block of data. IRQ=1 , it indicates that the controller has requested an interrupt.
and Disabling Interrupts, Handling Multiple Devices, Controlling Device Requests, Exceptions, Use Of Interrupts in Operating Systems, Pentium Interrupt Structure, Direct Memory Access, Busses, Interface Circuits, Standard I/O
Bus Master: The device that is allowed to initiate data transfers on the bus at any given time is called the bus master.
Bus Arbitration: It is the process by which the next device to become the bus master is selected and the bus mastership is transferred to it.
Types: There are 2 approaches to bus arbitration. They are, Centralized arbitration ( A single bus arbiter performs arbitration) Distributed arbitration (all devices participate in the selection of next bus master).
Centralized Arbitration:
Here the processor is the bus master and it may grants bus mastership to one of its DMA controller. A DMA controller indicates that it needs to become the bus master by activating the Bus Request line (BR) which is an open drain line. The signal on BR is the logical OR of the bus request from all devices connected to it. When BR is activated the processor activates the Bus Grant Signal (BGI) and indicated the DMA controller that they may use the bus when it becomes free. This signal is connected to all devices using a daisy chain arrangement. If DMA requests the bus, it blocks the propagation of Grant Signal to other devices and it indicates to all devices that it is using the bus by activating open collector line, Bus Busy (BBSY).
Fig:A simple arrangement for bus arbitration using a daisy chain
The timing diagram shows the sequence of events for the devices connected to the processor is shown. DMA controller 2 requests and acquires bus mastership and later releases the bus. During its tenture as bus master, it may perform one or more data transfer. After it releases the bus, the processor resources bus mastership
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Distributed Arbitration:
It means that all devices waiting to use the bus have equal responsibility in carrying out the arbitration process. Fig:A distributed arbitration scheme
Each device on the bus is assigned a 4 bit id. When one or more devices request the bus, they assert the Start-Arbitration signal & place their 4 bit ID number on four open collector lines, ARB0 to ARB3. A winner is selected as a result of the interaction among the signals transmitted over these lines. The net outcome is that the code on the four lines represents the request that has the highest ID number. The drivers are of open collector type. Hence, if the i/p to one driver is equal to 1, the i/p to another driver connected to the same bus line is equal to „0‟(ie. bus the is in low-voltage state).
Eg: Assume two devices A & B have their ID 5 (0101), 6(0110) and their code is 0111. Each devices compares the pattern on the arbitration line to its own ID starting from MSB. If it detects a difference at any bit position, it disables the drivers at that bit position. It does this by placing „0‟ at the i/p of these drivers. In our eg. „A‟ detects a difference in line ARB1, hence it disables the drivers on lines ARB & ARB0. This causes the pattern on the arbitration line to change to 0110 which means that „B‟ has won the contention.
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At time to, the master places the device address on the address lines & sends an appropriate command on the control lines. In this case, the command will indicate an input operation & specify the length of the operand to be read. The clock pulse width t1 – t0 must be longer than the maximum delay between devices connected to the bus. The clock pulse width should be long to allow the devices to decode the address & control signals so that the addressed device can respond at time t 1. The slaves take no action or place any data on the bus before t 1.
Fig:A detailed timing diagram for the input transfer
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The picture shows two views of the signal except the clock. One view shows the signal seen by the master & the other is seen by the salve. The master sends the address & command signals on the rising edge at the beginning of clock period (t 0 ). These signals do not actually appear on the bus until tam. Some times later, at tAS the signals reach the slave. The slave decodes the address & at t1, it sends the requested data. At t2, the master loads the data into its i/p buffer. Hence the period t2, tDM is the setup time for the masters i/p buffer. The data must be continued to be valid after t2, for a period equal to the hold time of that buffers.
Demerits:
The device does not respond. The error will not be detected.
Multiple Cycle Transfer:- During, clock cycle1, the master sends address & cmd infn/. On the bus‟ requesting a „read‟ operation. The slave receives this information & decodes it. At the active edge of the clock (ie) the beginning of clock cycel2, it makes accession to respond immediately. The data become ready & are placed in the bus at clock cycle3. At the same times, the slave asserts a control signal called „ slave-ready ‟. The master which has been waiting for this signal, strobes, the data to its i/p buffer at the end of clock cycle3. The bus transfer operation is now complete & the master sends a new address to start a new transfer in clock cycle4.
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Fig:Handshake control of data transfer during an input operation
The handshake protocol proceed as follows : At t 0 The master places the address and command information on the bus and all devices on the bus begin to decode the information At t 1 The master sets the Master ready line to 1 to inform the I/O devices that the address and command information is ready. The delay t 1 – t 0 is intended to allow for any skew that may occurs on the bus. The skew occurs when two signals simultaneously transmitted from one source arrive at the destination at different time. Thus to guarantee that the Master ready signal does not arrive at any device a head of the address and command information the delay t 1 – t 0 should be larger than the maximum possible bus skew.
At t 2 The selected slave having decoded the address and command information performs the required i/p operation by placing the data from its data register on the data lines. At the same time, it sets the “slave – Ready” signal to 1. At t 3 The slave ready signal arrives at the master indicating that the i/p data are available on the bus. At t 4 The master removes the address and command information on the bus. The delay between t 3 and t 4 is again intended to allow for bus skew. Errorneous addressing may take place if the address, as seen by some device on the bus, starts to change while the master – ready signal is still equal to 1. At t 5 When the device interface receives the 1 to 0 tranitions of the Master – ready signal. It removes the data and the slave – ready signal from the bus. This completes the i/p transfer.
and Disabling Interrupts, Handling Multiple Devices, Controlling Device Requests, Exceptions, Use Of Interrupts in Operating Systems, Pentium Interrupt Structure, Direct Memory Access, Busses, Interface Circuits, Standard I/O
In this diagram, the master place the output data on the data lines and at the same time it transmits the address and command information. The selected slave strobes the data to its o/p buffer when it receives the Master-ready signal and it indicates this by setting the slave – ready signal to 1. At time t 0 to t 1 and from t 3 to t 4 , the Master compensates for bus. A change of state is one signal is followed by a change is the other signal. Hence this scheme is called as Full Handshake. It provides the higher degree of flexibility and reliability. INTERFACE CIRCUITS
The interface circuits are of two types. They are Parallel Port Serial Port
Parallel Port:
The output of the encoder consists of the bits that represent the encoded character and one signal called vali d,whi c h indicates the key is pressed. The information is sent to the interface circuits,which contains a data register,DATAIN and a status flag SIN. When a key is pressed, the Valid signal changes from 0 to1,causing the ASCII code to be loaded into DATAIN and SIN set to 1. The status flag SIN set to 0 when the processor reads the contents of the DATAIN register. The interface circuit is connected to the asynchronous bus on which transfers are controlled using the Handshake signals Master ready and Slave-ready. A serial port used to connect the processor to I/O device that requires transmission one bit at a time. It is capable of communicating in a bit serial fashion on the device side and in a bit parallel fashion on the bus side.
STANDARD I/O INTERFACE
A standard I/O Interface is required to fit the I/O device with an Interface circuit. The processor bus is the bus defined by the signals on the processor chip itself. The devices that require a very high speed connection to the processor such as the main memory, may be connected directly to this bus. The bridge connects two buses, which translates the signals and protocols of one bus into another. The bridge circuit introduces a small delay in data transfer between processor and the devices.
