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Code No.: 15A05402/R
B.Tech. II Year II Semester Regular & Supplementary Examinations
May/June - 2019
Computer organization
( Common to CSE and IT )
Time: 3 Hours Max. Marks: 70
Part - a
(Compulsory Question)
**- - -
- Answer the following : (10 × 02 = 20 Marks)**
(a) What is the use of CPU? (Unit-I)
(b) Explain absolute addressing mode with example. (Unit-I)
(c) Describe Von Neumann rounding method for truncation. (Unit-II)
(d) Define multiphase clocking. (Unit-II)
(e) Explain read operation in SRAM cell. (Unit-III)
(f) Define seek time and latency in magnetic hard disks. (Unit-III)
(g) What are vectored interrupts? (Unit-IV)
(h) Explain the use of handshake control in data transfer on the bus. (Unit-IV)
(i) What are conditional code flags? (Unit-I)
(j) What is SISD? What are its advantages? (Unit-V)
Part - B
(Answer all five units, 5 × 10 = 50 Marks)
unit-i
- (a) What are the functions performed by the system software? (Unit-I, Topic No. 1.1.5)
(b) Explain about the logic instructions. (Unit-I, Topic No. 1.2.7)
OR
- (a) Draw and explain the single bus structure. (Unit-I, Topic No. 1.1.4)
(b) Represent the decimal values 26, 51, –10, as signed 7-bit numbers in 1’s complement binary format. (Unit-I, Topic No. 1.2.1)
unit-ii
- Draw and explain the block diagram of single-bus organization of the data path inside a processor. (Unit-II, Topic No. 2.2.1)
OR
- Illustrate about the Booth multiplication with a negative multiplier using suitable example. (Unit-II, Topic No. 2.1.4)
R
S o l u t i o n s
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unit-iii
- (a) Describe the internal organization of memory chips. (Unit-III, Topic No. 3.1)
(b) Explain about the virtual memory address translation. (Unit-III, Topic No. 3.7) OR
- (a) Discuss in detail about Set-Associative mapping function. (Unit-III, Topic No. 3.5)
(b) Explain how data is organized on magnetic tapes. (Unit-III, Topic No. 3.9)
unit-iV
- Describe the interrupt priority schemes handing simultaneous requests from multiple devices. (Unit-IV, Topic No. 4.2)
OR
- What is DMA? Explain the working of DMA with a neat sketch. What are its advantages? (Unit-IV, Topic No. 4.4)
unit-V
- Illustrate the three ways of implementing a multiprocessor system. (Unit-V, Topic No. 5.2.3)
OR
- (a) Describe how to handle data hazards in software. (Unit-V, Topic No. 5.1.2)
(b) Explain in detail about the Hypercube networks. (Unit-V, Topic No. 5.2.4)
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Working
In the above figure, the transistors act as a switch performing open and close operations. The operations of these transistors are controlled by horizontal word line running across the circuit. Whenever, the word line is grounded, the transistors remain in closed state hence the latch circuit retains or holds their states.
In order to read the state 1 of transistors, ‘ W ’ is made high, as a result the transistors get closed causing the signal ‘ i ’ to go high correspondingly ‘ i ’’ to go low. Similarly, to read state 0, ‘ i ’ is made low with ‘ i ’’ to go high.
(f) Define seek time and latency in magnetic hard disks.
Answer : May/June-19(R15), Q1(f)
For answer refer May/June-2017(R15), Q1(f), Topics: Seek Time, Latency Time/Rotational Delay.
(g) What are vectored interrupts?
Answer : May/June-19(Rx15), Q1(g)
For answer refer May/June-2017(R15), Q1(g). (h) Explain the use of handshake control in data transfer on the bus.
Answer : May/June-19(R15), Q1(h)
The asynchronous bus controls data transfer using handshake protocol, which inturn makes use of two timing control signals.
Master-ready and slave-ready , instead of a common clock. The master-ready signal is asserted by the master to inform all the devices that it has placed the slave’s address and the command (i.e., input or output operation) on the bus. The slave-ready signal is asserted by the slave when it responds to the master’s request. The two different operations that can be performed on an asynchronous bus are,
- Input operation (i.e., Data transfer from the slave to the master)
- Output operation (i.e., Data transfer from the master to the slave). (i) What are conditional code flags?
Answer : May/June-19(R15), Q1(i)
Condition Code Flags
The conditional branch instructions use few flags called “condition code flags” in order to test the condition. Generally, there are four conditional code flags. They are, N(Negative) flag, Z(Zero) flag, V(Overflow) flag and C(Carry) flag. These flags are together stored in a register called “condition code register” or “status register”, using one bit for each flag. They are set/reset by the processor depending upon the result of an operation.
1. N Flag
The N flag indicates whether the result of an arithmetic or logic operation is negative. It is set to 1 when the result is negative. Otherwise, it is cleared to 0.
2. Z Flag
The Z flag indicates whether the result of an arithmetic, logic or even a data transfer operation is zero. It is set to 1 when the result is zero. Otherwise, it is cleared to 0.
3. V Flag
The V flag indicates whether the size of the result of an arithmetic operation is more than the operand size used by the system. It is set to 1 when the arithmetic overflow occurs. Otherwise, it is cleared to 0.
4. C Flag
The C flag indicates whether the leftmost bit of the result generates a carry. It is set to 1 when a carry is generated (from the leftmost bit) during an arithmetic operations. Otherwise, it is cleared to 0.
(j) What is SISD? What are its advantages?
Answer : May/June-19(R15), Q1(j)
SISD
For answer refer Unit-V, Q22, Topic: Single Instruction Stream, Single Data Stream (SISD).
Advantages of SISD
- The consumption of power is less.
- The communication between multiple cores is not complex.
- The SISD can be implemented in any CPU.
Part - B
unit-i
Q2. (a) What are the functions performed by the system software?
Answer : May/June-19(R15), Q2(a)
For answer refer Unit-I, Q18(a)(b).
(b) Explain about the logic instructions.
Answer : May/June-19(R15), Q2(b)
For answer refer Unit-I, Q39.
oR
Q3. (a) Draw and explain the single bus structure.
Answer : May/June-19(R15), Q3(a)
For answer refer Unit-I, Q16.
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(b) Represent the decimal values 26, 51, –10, as signed 7-bit numbers in 1’s complement binary format.
Answer : May/June-19(R15), Q3(b)
Decimal Values of 1's Complement
(a) 26
The equivalent binary number of ‘26’ is, 11010
It is given that the length of the number should be 7. So, add two 0's at the starting to make the length of signed number as 7.
Therefore, the 1's complement of 7 becomes 0011010.
(b) 51
The equivalent binary number of 51 is 110011.
It is given that, the length of the number should be 7. So, add one 0 at the starting to make the length of the signed number as 7.
Therefore, the one’s complement of 51 becomes 0110011.
(c) –
The equivalent binary number – 10 will be calculated as,
Initially, calculate the binary equivalent of +10 i.e., 1010
Thus, the binary equivalent of –10 will be 1001010.
Now, the 1's complement of 51 becomes 1110101.
unit-ii
Q4. Draw and explain the block diagram of single-bus organization of the data path inside a processor.
Answer : May/June-19(R15), Q
For answer refer Unit-II, Q26.
oR
Q5. Illustrate about the Booth multiplication with a negative multiplier using suitable example.
Answer : May/June-19(R15), Q
Given,
Multiplicand ( A ) = 110011
Multiplier ( B ) = 101100
Here,
Multiplicand ( A ) and Multiplier ( B ) are negative numbers whose decimal numbers can be obtained by taking 2’s complement of both A and B. Thus,
2’s complement of multiplicand = 1’s complement of Multiplicand +
= 001100 + 1
( A r^ + 1 )= 001101
= (– 13) 2
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i.e., In the above multiplier, Pair 1 ® 101 = – 1 Par 2 ® 110 = – 1 Pair 3 ® 000 = 0 The multiplication of the multiplicand 110011 and the bit pairs –1, –1 and 0 is. 1 1 0 0 1 1 × –1 –1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 * * 0 0 0 1 1 0 1 * * * *
0 0 1 0 0 0 0 0 1 0 0
1 1 1 1
® 2's complement of Multiplicand
\ The result is (001 00000100) 2 = (260) 10
unit-iii
Q6. (a) Describe the internal organization of memory chips.
Answer : May/June-19(R15), Q6(a)
For answer refer Unit-III, Q12. (b) Explain about the virtual memory address translation.
Answer : May/June-19(R15), Q6(b)
For answer refer Unit-III, Q38. oR
Q7. (a) Discuss in detail about Set-Associative mapping function.
Answer : May/June-19(R15), Q7(a)
For answer refer Unit-III, Q30, Topic: Set Associative Mapping Technique. (b) Explain how data is organized on magnetic tapes.
Answer : May/June-19(R15), Q7(b)
For answer refer Unit-III, Q42.
unit-iV
Q8. Describe the interrupt priority schemes handing simultaneous requests from multiple devices.
Answer : May/June-19(R15), Q
When two or more requests arrive at the same time from various sources, the priority interrupt system establishes the priority for them in order to determine which condition need to be serviced first. The high speed transfers such as magnetic disks are assigned high priority whereas, low speed devices such as keyboards are given low priority. Once the priorities are set, the highest priority devices are serviced first.
According to this method, when interrupts arise in a program, they will be branched to a common branch address. If this program want to handle the interrupts, it will proceed from this branch address. This branch address is the starting address of an interrupt service routine, which is a program that tests all the interrupt sources in a sequential order and will then branch to a single service routine belonging to a source with the highest priority among all the interrupt sources. Thus, when a program branches to this routine, the required interrupt sources are polled in a sequential order. These sources are then tested in some order, and this order corresponds to their priority levels. That is, the source that has been tested first will have the highest priority, and the sources that are tested later have lower priorities. If the interrupt signal of the highest-priority source is ‘ON’, the control will branch to the corresponding service routine or else, the next source is tested and this process continues until all the sources have been tested.
oR
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Q9. What is DMA? Explain the working of DMA with a neat sketch. What are its advantages?
Answer : May/June-19(R15), Q
DMA
For answer refer Unit-IV, Q13, Topic: Direct Memory Access (DMA).
Working of DMA
For answer refer Unit-IV, Q32, Topic: Operation of DMA.
Advantages of DMA
For answer refer Unit-IV, Q8.
unit-V
Q10. Illustrate the three ways of implementing a multiprocessor system.
Answer : May/June-19(R15), Q
For answer refer Unit-V, Q24.
oR
Q11. (a) Describe how to handle data hazards in software.
Answer : May/June-19(R15), Q11(a)
For answer refer Unit-V, Q15.
(b) Explain in detail about the Hypercube networks.
Answer : May/June-19(R15), Q11(b)
For answer refer Unit-V, Q28, Topic: Hypercube Networks.
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unit-iii
- A digital computer has a memory unit of 64K*16 and a cache memory of 1K words. The cache uses direct mapping with
a block size of four words. How many bits are there in the tag, index, block and word fields of the address format? How many blocks can the caches accommodate? (Unit-III, Topic No. 3.5)
OR
- Discuss how the virtual address is converted into real address in a paged virtual memory system with a neat sketch.
(Unit-III, Topic No. 3.7)
unit-iV
- Exemplify the use of vectored interrupts in processes. Why priority handling is desired in interrupt controllers? How does
the different priority scheme work? (Unit-IV, Topic No. 4.2)
OR
- Draw the typical block diagram of a DMA controller and explain how it is used for direct data transfer between memory
and peripherals. (Unit-IV, Topic No. 4.4)
unit-V
- Exemplify how pipeline helps to speed up the processor. Discuss the types of hazard that have to be taken care of in a
pipelined processor. (Unit-V, Topic No. 5.1.1)
OR
- What is the purpose of parallel processing? Categorize and discuss the various forms of parallel processing with a neat
sketch. (Unit-V, Topic No. 5.2.1)
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Part - a
Q1. (a) Compare and contrast RISC & CISC.
Answer : May/June-18(R15), Q1(a)
RISC CISC
- Simple instructions take one cycle. An average CIP is less than 1.5. 1. Complex instructions take multiple cycles. An average CPI is between 2 and 15.
- Very few instructions refer memory. 2. Most of instructions may refer memory.
- Instructions are executed by hardware. 3. Instructions are executed by microprogram.
- Fixed format instructions. 4. Variable format instructions.
- Few instructions. 5. Many instructions.
- Few addressing modes and most instructions have register to register addressing mode. 6. Many addressing modes.
- Complex addressing modes are synthesized in software. 7. Supports complex addressing modes.
- Multiple register set. 8. Single register set.
- Highly pipelined. 9. Not pipelined or less pipelined.
- Complexity in the compiler. 10. Complexity in the microprogram.
(b) What are the basic functional units of a computer?
Answer : May/June-18(R15), Q1(b)
For answer refer Unit-I, Q10, Topic: Functional Units.
(c) Perform the subtraction operation for the following numbers: (63) 10 and (– 17) 10.
Answer : May/June-18(R15), Q1(c)
Binary equivalent of (63) 10 = (00111111) 2
Binary equivalent of (– 17) 10 = (11101111) 2
Step 1
Compute the 1’s compliment of subtrahend i.e., 00010000.
Step 2
Add 1 to the 1’s compliment. 0 0 0 1 0 0 0 0
0 0 0 1 0 0 0 1
Step 3
Now, add the minuend (i.e., 00111111) to 00010001. 0 0 1 1 1 1 1 1 0 0 0 1 0 0 0 1 0 1 0 1 0 0 0 0
\ The subtraction of (63) 10 and (– 17) 10 = (80) 10.
SolutionS to may/June-2018, (r15), Qp
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(j) Mention few interconnection networks that are commonly used in multiprocessors.
Answer : May/June-18(R15), Q1(j)
The four interconnection networks used in microprocessors are as follows, (i) Hypercube networks (ii) Ring networks (iii) Tree networks and (iv) Mesh networks.
(i) Hypercube Networks
A hypercube interconnection system is used to implement a network which consist of 2 n^ nodes in an n -dimensional cube. This structure reflects loosely coupled multiprocessor system with each node correspond to a processor. Moreover the processor may associate certain additional circuitry such as I/O interfaces and can also maintain local memories etc.
(ii) Ring Networks
In ring topology, the computers are connected in the form of a ring. Each node has exactly two adjacent neighbours. In order to send data to a distant node on a ring, it is passed through many intermediate nodes to reach to its ultimate destination.
(iii) Tree Networks
Tree topology is a hierarchy of various hubs. All the nodes are connected either to one hub or to the other. There is a central hub to which only a few nodes are connected directly.
(iv) Mesh Networks
A mesh topology is also called as a complete topology. In this topology, each node is connected directly to every other node in the network. That is, if there are n nodes then there would be n ( n – 1)/2 physical links in the network.
Part - B
unit-i
Q2. give a short sequence of machine instructions for the task: “Add the contents of memory location A to those of location B and place the answer in location C”. Instructions load loC, Ri and store R (^) i loC are the only instructions available to transfer data between the memory and general purpose register R (^) i. Do not destroy the contents of either location A or B.
Answer : May/June-18(R15), Q
The sequence of machine instructions for the given task are,
- STORE Reg1, A
- STORE Reg2, B
- ADD Reg3, Reg1, Reg
- LOAD C, Reg In the above instruction set, Instruction 1 obtains the contents of memory location A and stores in a ‘Reg1’ register. Instruction 2 obtains the contents of memory location B and stores in a ‘Reg2’ register. Instruction 3 adds the contents of both the ‘Reg1’ and ‘Reg2’ registers and stores in ‘Reg3’ register. Instruction 4 loads the contents of ‘Reg3’ in the memory location C. oR
Q3. Discuss about the various types of addressing modes with examples in detail.
Answer : May/June-18(R15), Q
For answer refer Unit-I, Q33, Topic: Types of Addressing Modes.
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unit-ii
Q4. Multiply the following unsigned numbers using Booth’s algorithm: Multiplicand = 1000, multiplier = 0011.
Answer : May/June-18(R15), Q
Multiplicand (B) ← 1000 (8) Multiplier (C) ← 0011 (3) Steps A C 0 C (^) – 1 Operation Count
0000 0011 0 Initial 100 Step 1 (^1000 0011 0) A ← A + B + 1 1100 0001 1 Arithmetic right shift 011 Step 2 1110 0000 1 Arithmetic right shift 010 Step 3 0110 0000 1 A ← A + B 0011 0000 0 Arithmetic right shift 001 Step 4 0001 1000 0 Arithmetic right shift 000 Result 0001 1000 = 24
oR
Q5. Draw the organization of the typical hardwired control unit and explain the various functions performed by the various blocks.
Answer : May/June-18(R15), Q
For answer refer Unit-II, Q35.
unit-iii
Q6. A digital computer has a memory unit of 64K16 and a cache memory of 1K words. The cache uses direct mapping with a block size of four words. How many bits are there in the tag, index, block and word fields of the address format? How many blocks can the caches accommodate?*
Answer : May/June-18(R15), Q
Given that, Memory size = 64 K × 16 = 64 × 1024 = 65536 = 2^16 Cache memory = 1 K = 1 × 1024 = 1024 = 2^10 Word size = 4 words The address format of direct mapping is,
TAG Field
Index Field Block Field Word Field
N-bit-cache address
m-bit memory address
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When a particular process is being executed, a register holds the starting address of page table for that process. Page number of a virtual address is used to index the table and look up the corresponding frame number. This is combined with the offset portion of virtual address to produce desired real address as shown in the figure. Typically, the page number field is longer than the frame number field ( n > m ).
Here, the disadvantage is that the amount of memory used by the page tables alone can be high. To overcome this, virtual memory schemes store page tables in virtual memory than in real memory and so the page tables are also subjected to paging. When a process is running, a part of the page table including page table entry of the currently executing page must be in main memory. Some processors make use of a two level scheme to organize large page tables. In this, there is a page directory in which each entry points to a page table is present. So, if length of page directory is ‘ x ’ and if maximum length of it is ‘ y ’, a process will consist upto x * y pages. Usually, length of page table is restricted to be equal to one page.
unit-iV
Q8. Exemplify the use of vectored interrupts in processes. Why priority handling is desired in interrupt controllers? How does the different priority scheme work?
Answer : May/June-18(R15), Q
Use of Vectored Interrupts
Vectored interrupt mechanism enhances the interrupt process by adding an “Interrupt vector array”, which stores the interrupt request number of each device. Each time an interrupt occurs, it displays IRQ devices, that can be loaded into the interrupt vector array in the form of index. Now, the OS preloads every single location in the interrupt using a pointer to manage the interrupt. This can be found in the below given format.
Interrupt – Vector [i] i = 0, 1, 2,... n.
device n–
device 2 device 1 device 0
Figure (1): Interrupt Vector Array Interrupt vector array shows the method of finding the interrupt of a given device with a processor. When multiple devices raise interrupt request concurrently, the task of the processor becomes difficult as it has to decide which request must be handled first and which one should be handled next. In such situations, the processor employs interrupt priorities where in priorities are assigned to the devices. And the device which has the highest priority is serviced first. These priorities are generally assigned using priority handles.
Priority Schemes
Various priority management techniques are,
1. Polling
It is a procedure of determining the highest-priority source among all the available sources with the help of a software means. According to this method, when interrupts arise in a program, they will be branched to a common branch address. If this program want to handle the interrupts, it will proceed from this branch address. This branch address is the starting address of an interrupt service routine, which is a program that tests all the interrupt sources in a sequential order and will then branch to a single service routine belonging to a source with the highest priority among all the interrupt sources. Thus, when a program branches to this routine, the required interrupt sources are polled in a sequential order. These sources are then tested in some order, and this order corresponds to their priority levels. That is, the source that has been tested first will have the highest priority, and the sources that are tested later have lower priorities. If the interrupt signal of the highest-priority source is ‘ON’, the control will branch to the corresponding service routine or else, the next source is tested and this process continues until all the sources have been tested.
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2. Daisy-chaining Priority
Daisy-chaining priority is a priority management technique where all the devices which are capable of interrupting a given processor are placed sequentially and are provided with certain priorities (i.e., number to recognize the importance of a device). Here, the devices with highest priority remains nearer to the processor while the devices with low priority are placed away from the processor.
Figure (2) demonstrate the concept of Daisy-chaining priority.
Figure (2): Daisy-chain Priority Interrupt
In the above figure, there is a single processor supporting four I/O devices capable of interrupting the processor. Each of these I/O devices posses four connections, with first two connections i.e., ‘I’ and ‘O’ indicating priority input and priority output respectively and the other two represents vector address (to place the requirement of interrupt) and a connection to INT line which is running through the processor. Apart from INT signal, the processor maintains the vector address signal and interrupt acknowledgement signal in order to collect the interrupt information and to grant the interrupt request. In case of no interrupts, the interrupt request line remains high (1). If the processor senses a low signal on it’s interrupt request line, it analyzes that the interrupt has occurred and responds it through enabling it’s Interrupt Acknowledgment line (INTACK). Initially the INTACK line connects to D1 since it is a device with the highest priority. If D1 is not interested in an interrupt, it simply regrets by placing a value ‘0’ at the output terminal ‘O’. D2, on receiving a value ‘0’ at its ‘I’ assumes that it can request for an interrupt and places it’s vector address on the processor’s data bus and assigns a value ‘1’ at ‘O’ indicating the device D3 that, the INTACK line is already held by other devices. It may also happen that, the interrupt may be in pending state. In such conditions, the given device disables the INTACK signal required to be transmitted to other devices by placing ‘1’ at it’s ‘O’.
The device which receives interrupt acknowledgment from the CPU gets the highest priority in daisy chaining. The nearer the device to the CPU, the higher will be its priority. User can assign priority by physically connecting devices in some order.
Consider an example of internal logic of one-stage of diary priority arrangement as shown in figure (3).
Figure (3): One Stage of Daisy Chaining
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Q9. Draw the typical block diagram of a DMA controller and explain how it is used for direct data transfer between memory and peripherals.
Answer : May/June-18(R15), Q
For answer refer Unit-IV, Q32.
unit-V
Q10. Exemplify how pipeline helps to speed up the processor. Discuss the types of hazard that have to be taken care of in a pipelined processor.
Answer : May/June-18(R15), Q
Pipeline to Speed up the Processor
Pipeline helps to speed up the processor by taking up all the segments of the processor and the processor do the maximum possible work in a particular time period. It also increases the throughput of the instructions and decreases the cycle time of a processor.
Example
For answer refer Unit-V, Q9, Topic: Example.
Types of Hazard
For answer refer Unit-V, Q13.
oR
Q11. What is the purpose of parallel processing? Categorize and discuss the various forms of parallel processing with a neat sketch.
Answer : May/June-18(R15), Q
Purpose of Parallel Processing
The purpose of parallel processing is to improve the throughput by distributing the work load among multiple processors and disks. It also provides improved performance by reducing clocks per instruction (CPI).
Various Forms of Parallel Processing
For answer refer Unit-V, Q22.
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