Docsity
Docsity

Prepare for your exams
Prepare for your exams

Study with the several resources on Docsity


Earn points to download
Earn points to download

Earn points by helping other students or get them with a premium plan


Guidelines and tips
Guidelines and tips

Computer architecture and 8086 architecture, Slides of Computer Architecture and Organization

these slides would be really helpful in studying 8086 pin diagram and computer organization.

Typology: Slides

2016/2017

Uploaded on 05/13/2017

jasleenkaur2200
jasleenkaur2200 🇮🇳

1 document

1 / 38

Toggle sidebar

This page cannot be seen from the preview

Don't miss anything!

bg1
University Institute of Engineering (UIE)
Computer Organization and
Architecture
Subject
Coordinator:
Akwinder Kaur
Subject Code: CST-259
TOPIC: Instruction Set
Architecture
pf3
pf4
pf5
pf8
pf9
pfa
pfd
pfe
pff
pf12
pf13
pf14
pf15
pf16
pf17
pf18
pf19
pf1a
pf1b
pf1c
pf1d
pf1e
pf1f
pf20
pf21
pf22
pf23
pf24
pf25
pf26

Partial preview of the text

Download Computer architecture and 8086 architecture and more Slides Computer Architecture and Organization in PDF only on Docsity!

Computer Organization and

Architecture

Subject Coordinator: Akwinder Kaur

Subject Code: CST-

TOPIC: Instruction Set

Architecture

Department of Computer and Communication Engineering (C

  • (^) To familiarize students with the concepts related to instructions
  • (^) To learn the various levels of programming languages
  • (^) To know the different instruction set architectures

Learning Objectives

(CSE)

  • (^) Instruction set architecture(ISA) is the set of processor design techniques used to implement the instruction work flow on hardware.
  • (^) In more practical words, ISA tells you that how your processor going to process your program instructions.

Instruction Set Architecture

(CSE)

Instruction Set Architecture

Fig 1: Instruction set architecture [1]

(CSE)

Categories of Programming

Language

Fig 2: Categories of Programming language [2]

(CSE)

Assembly Language

  • (^) Assembly language is a middle-level programming language for a computer or other programmable device specific to a particular computer architecture in contrast to most high-level programming languages, which are generally portable across multiple systems.
  • (^) Assembly language is converted into executable machine code by a utility program referred to as an assembler.
  • (^) Assembly language consist of various instruction like ADD, LDA, STA, MOV, MVI, HLT etc.

(CSE)

Instruction

  • (^) Operation Code(OpCode) The operation code of an instruction is a group of bits that define such operations as add, subtract, multiply, shift and complement. Example: ADD, LDA, STA, MOV, MVI, HLT etc.
  • (^) Operand Data: Value/Register/Memory Addressing Modes

(CSE)

Addressing Modes

  • (^) How data is being assigned/addressed to

instructions is called addressing mode.

  • (^) Generally addressing modes are

divided as:

  • (^) Direct addressing(Figure: b)
  • (^) Indirect addressing(Figure: c)
    • (^) Effective address?
  • (^) Effective address(EA)?
  • (^) EA = Base Address + Given Address

(CSE)

Types: Addressing Modes

  • (^) Implied Mode- operands are specified implicitly in the instruction itself.
  • (^) Immediate Mode- the address field contains the operand itself instead of the address of the operand.
  • (^) Register Mode- the address field contains the address of a CPU register which contains the operand.
  • (^) Register Indirect Mode- the address field contains the address of a register which holds the memory address of the operand.

(CSE)

Types: Addressing Modes

  • (^) Relative Mode: Relative address means an address specified by indicating its distance from another address, called the base address.
  • (^) Index/Based Indexed Mode: It means an address specified by indicating its distance from another base address.

(CSE)

Computer Instructions Formats

Fig 5: Basic Computer instruction formats [3]

(CSE) Table 1: Basic Computer Instructions [3]

(CSE)

Instruction Cycle: Fetch Phase

(CSE) Instruction Cycle: Fetch Phase Fig 5: Register transfers for the fetch phase [3]