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Main points of this lecture are: Computer Architecture, Conventional Wisdom, Memory Wall, Simpler Processors, Uniprocessor Performance, Brick Wall, Power Wall, Sea Change in Chip Design, Procrastination, Classes of Computers, Critical Interface
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Crossroads: Uniprocessor Performance
From Hennessy and Patterson, Architecture: A Quantitative Approach Computer , 4th edition, October, 2006
r0^0 r1° °° r PC lo hi
Programmable storage 2^32 x bytes 31 x 32-bit GPRs (R0=0) 32 x 32-bit FP regs (paired DP) HI, LO, PC
Data types? Format? Addressing Modes?
Arithmetic logical Add, AddU, Sub, SubU, And, Or, Xor, Nor, SLT, SLTU, AddI, AddIU, SLTI, SLTIU, AndI, OrI, XorI, LUI SLL, SRL, SRA, SLLV, SRLV, SRAV Memory Access LB, LBU, LH, LHU, LW, LWL,LWR SB, SH, SW, SWL, SWR Control J, JAL, JR, JALR BEq, BNE, BLEZ,BGTZ,BLTZ,BGEZ,BLTZAL,BGEZAL
32-bit instructions on word boundary
“... the attributes of a [computing] system as seen by the programmer, i.e. the conceptual structure and functional behavior, as distinct from the organization of the data flows and controls the logic design, and the physical implementation.” – Amdahl, Blaauw, and Brooks, 1964
SOFTWARE -- Organization of ProgrammableStorage -- Data Types & Data Structures:Encodings & Representations -- Instruction Formats -- Instruction (or Operation Code) Set -- Modes of Addressing and Accessing Data Items and Instructions -- Exceptional Conditions
Comp. Arch. is an Integrated Approach
Design
Analysis
Architecture is an iterative process:
Creativity
Good Ideas Mediocre Ideas
Cost / Performance Analysis
CIS 580 CIS 600
CIS 650
How to build it Implementation details
Why, Analysis, Evaluation
Alternative Course Compilers
Strong Prerequisite
Basic knowledge of the organization of a computer is assumed!
What Computer Architecture brings to Table
I n s t r.
O r d e r
Time (clock cycles)
Ifetch Reg ALU DMem Reg
Ifetch Reg ALU DMem Reg
Ifetch Reg ALU DMem Reg
Ifetch Reg ALU DMem Reg
Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7
I n s t r. O r d e r
Time (clock cycles) Ifetch Reg ALU DMem Reg Ifetch Reg ALU DMem Reg Ifetch Reg ALU DMem Reg Ifetch Reg ALU DMem Reg