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E X P E R I M E N T
COMBINATIONAL LOGIC
CIRCUITS
VERSION F
In this experiment, you will design, implement and verify two combinational logic circuits. One circuit implements a very simple logic function and the other implements a BCD-to-7-segment code converter. After performing this experiment, you should be able to:
- Design combinational circuits for implementation in an FPGA,
- Use simulation to verify circuit function,
- Use timing analysis and simulation to identify a worst case delay path,
- Use an FPGA-prototyping system to verify circuit function, and
- Perform circuit-level propagation delay measurements
3-1 PRELAB
FPGA I MPLEMENTATION AND DELAY
In the Altera Cyclone technology which we are using, logic functions are decomposed by the implementation tools into 4-input subfunctions. (Even though you are drawing gates in your schematic, what you see is NOT what you get!) Each subfunction is then implemented by a truth table defined by programming the SRAM that defines the FPGA’s functionality. Each of the truth tables has a delay which contributes to the delay down one or more paths from inputs to outputs of the function being implemented. In addition, the connections in the FPGA between the inputs, truth tables, and outputs pass through buffers, multiplexers and pass transistors as determined by the circuit specification and the routing paths determined by the implementation tools.
The decomposition into subfunctions combined with the routing of the interconnections between them yields considerable uncertainty in the propagation delay from input to output of an implemented circuit. A sophisticated user of the tools may use constraints to specify the maximum delays allowable, forcing the tools to attempt to meet or better these delays. Whether or not delays are specified, it is useful to know either whether delay specifications are met or some measure of the delays present. Since most combinational circuits are placed in a sequential environment, there is usually interest in the worst case delay that can occur in the operation of the circuit from any combinational logic input to any combinational logic output (equivalently, in the sequential circuit: from input to output, from input to flip-flop, from flip-flop to flip-flop, and from flip-flop to output). Worst case delay estimates are determined by adding up the maximum expected delays through the combinational circuit including both logic and interconnections. Because of the uncertainty discussed in the previous paragraph, worst case delay can be known only after the implementation process has been completed including the decomposition into subfunctions and the interconnect routing.
In this experiment, we will construct two circuits to be discussed later. With first circuit we will investigate some of
XBAR
Y
Figure 1 Simple Circuit
- Give the truth table for this circuit.
- Assume that this circuit was constructed by interconnecting real devices (an integrated circuit inverter and NAND gate). If we applied a square wave signal to X, what would output Y look like?
BCD- TO-7- SEGMENT CODE CONVERTER
The BCD-to-7-segment code converter (commonly referred to as a BCD-to-7-segment decoder) is used to convert a binary coded decimal (BCD) value to the appropriate segment pattern for a 7-segment display. Since BCD values are 4-bit numbers in the range 0-9, how we treat the remaining possible values of 10-15 will impact our design. While we might consider those values to be ‘don’t-cares’, simplifying the logic required compared to making the display blank for those values, for this lab you will design the decoder so that it displays a specific pattern for all non-BCD values. The segments in the display are typically identified in industry by the letters a-g, corresponding to the segments shown below.
f
a b g e c d Figure 2 Seven-Segment Display Convention
So, the input to your circuit will be a 4-bit number (label these signals D3, D2, D1, D0; with D3 being the most significant bit), and there will be 7 outputs (label these signals A, B, C, D, E, F, G to correspond to the segment pattern shown above) that will light the display in the patterns shown below in Figure 3 for all valid inputs. All invalid inputs shall be considered as don’t-care conditions in the logic design.
Figure 3 Seven-Segment Display Patterns
To make our BCD-to-7-segment decoder design easier to use and to easily create multiple instances of it, we will also embed it in a hierarchy block, and then make connections to the block in order to test our design.
- Sheet BCD_7SEG: On sheet BCD_7SEG, you are to implement your BCD-to-7-segment decoder circuit that you designed as specified above. Also, rather than using inverters, you can use n-input gates from the library having n bubbled (inverted) inputs. For example, the gate BAND3 has three inputs that are inverted by bubbles, permitting implementation of terms such as X2 • X1•X 0 without using inverters. Use input or output pins as appropriate, setting the pin names to be D3-D0 and A-G as appropriate. When your circuit is complete, select File Æ Create/Update Æ Create Symbol Files for Current File. Now, your BCD-to-7- segment decoder will be available to use as a component in other schematics. (It has become a part of the library components for this project.)
- Sheet BCD_TEST: On Sheet BCD_TEST, you are to design a circuit that uses the BCD_7SEG block, and that connects the inputs to the DIP switches S1_1 - S1_4 and the outputs to the LED display 1 (DIS1) on the FPGA board. Place your BCD_7SEG block (it will be available in the Symbol Toolbox window under the library PROJECT ), and then connect the inputs and outputs as listed below. Name the pins as shown below. Do the same for the outputs. This will assign pin numbers to those nets automatically using the pin locations you imported into the project. This allows us to specify physical pins by using names that make sense to us, instead of having to look up the pin numbers each time. Pin connected to… Use net name D3 S1_ D2 S1_ D1 S1_ D0 S1_ A DIS1_A B DIS1_B C DIS1_C D DIS1_D E DIS1_E F DIS1_F G DIS1_G
NETLIST GENERATION AND F UNCTIONAL SIMULATION
- Set the current sheet (BCD_TEST) as the Top level entity in the hierarchy. This can be done by selecting Project Æ Set as Top-Level Entity.
- Functionally simulate the circuit for all possible input combinations: Select and add S1_4, S1_3, S1_2, S1_1, and DIS1_A through DIS1_G as signals. Select individual signals and place them in logical order in the Waveform Editor. Use Overwrite Clock in the Tools panel on the left for S1_1 and set its period to 160ns. Similarly add Clock simulators to S1_2 with 80ns period, S1_3 with 40ns period, and S1_
- If the simulation is correct, go back and print the necessary copies of the schematic sheets. If not, correct the design and re-simulate and print later.
- Annotate the simulation so that it is clearly shown that the circuit functions correctly.
- Print out your simulation on one page. Be careful to not print out large number of pages of output and to use Landscape.
IMPLEMENTATION AND REPORT ANALYSIS
- Click on Start Compilation from the Processing menu. This implements the overall design.
- Check the Pin-out File to make sure that all pins have been assigned correctly.
TIMING SIMULATION
- Perform a timing simulation on the design using the same signals and waveforms you used for the functional simulation above. Make sure the simulation is set for Timing and not Functional.
- Execute the simulation and verify that the outputs (except for some delays and glitches) are identical to those for the functional simulation.
- Do not close the timing simulation window.
WORSE CASE DELAY SIMULATION
- Examine the Timing Analyzer Summary and tpd tabs of the Compilation Report for the maximum delay from any of the inputs, S1_3, S1_2, S1_1 and S1_0 to any of the outputs, DIS1_A through DIS1_G. The input for this maximum delay will be referred to as the path source , Xi, and the output will be the path destination , Yj.
- By examining the truth table for function Yj, find all value sets for the three input variables other than Xi, such that when Xi changes between 0 and 1, Yj also changes value. For example, if Xi is S1_3 and truth table rows S1_3 = 1, S1_2 = 1, S1_1 = 0, S1_0 = 1, Yj = 0 and S1_3 = 0, S1_2 = 1, S1_1 = 0, S1_0 = 1, Yj = 1 appear, then S1_2, S1_1, S1_0 = (1,0,1) is a value set. Since a change in Xi causes Yj to change when this value set is applied, the delay can be measured from Xi to Yj. If there are no such value sets, then the delay identified cannot be reliably measured since the value before and after the delay is the same. In this case, pick the next longest delay and repeat the process for finding value sets.
Provide answers to the following.
- What is the maximum delay for the decoder?
- What input Xi is the path source?
- What output Yj is the path destination?
- What are all input variable sets and their values for which a change in Xi as determined above produces a change in Yj?
- Perform a new timing simulation for all inputs and output Yj only, applying each of the input variable set values in succession with the path source Xi changing from 0 to 1 to 0 for each value set. This will let us identify the delays that correspond to each possible path.
- Open the Simulation Report. Measure the delays from Xi to Yj for each input variable set. The simplest way to do this is to move the time bar so that it is at the point where the input Xi changes, then place the mouse cursor on the point where the output changes and read the interval at the top of the window. Be sure to zoom in on the waveform to get an accurate answer.
- Find the maximum delay time that is measured and identify the value set for which it occurs. This pair is the one that causes the signal to propagate down the longest path from Xi to Yj.
3) CHECKPOINT: Have your instructor observe the waveforms.
PROJECT BCD
PERFORMING FUNCTIONAL TEST
First, we will apply inputs to the BCD decoder using the DIP switches and observe the seven segment display to verify the functional correctness of your decoder. First, we will load the bcd_init.sof file into the FPGA.
- In Quartus, open your bcd project. Configure the FPGA by running Tools Æ Programmer.
- Connect the D3-D0 inputs of the oscilloscope to the FPGA board header pins corresponding to S1_1 - S1_4 so that you can verify the actual input to the FPGA.
- Test your circuit using all possible input combinations and observing the LED display DIS1. 4) CHECKPOINT: Have your instructor observe the output of your decoder.
DECODER DELAY TEST
We now want to evaluate the worst case time delay through the decoder that we observed during timing simulation. Because there are only four input variables and three of them are fixed, this will be greatly simplified. We will use a clock signal to stimulate the input with the longest delay, and the DIP switches to set the other inputs.
- Perform the POWER DOWN sequence.
- Set the DIP switch corresponding to variable Xi identified in the timing simulation as the source of a longest path to the OFF position. Then, connect the oscillator signal ( CLK0) output to the Xi input by using a blue jumper from the CLKIN pin of JP12 to the pin on JP7 corresponding to the Xi DIP switch. (Refer to the Board Locations document if you can’t find these on the FPGA board.) Ensure that the DIP switch corresponding to variable Xi remains in the OFF position as long as this connection is made.
- Set the remaining DIP switches to give you the value set that you identified in the prelab that is associated with the worst case delay.
- Connect the ground clips from the scope probes to the GROUND header on the FPGA board.
- Connect the oscilloscope channel A1 probe to CLKIN pin of JP12.
- Connect the oscilloscope channel A2 probe to Yj, the variable that is the destination for the longest path. The signals to the displays are all available on JP8.
- Perform the POWER DOWN sequence.
- Very carefully remove all leads including the power from the board. Put the board and the power supply in the bottom of the tray and place the three probes and the bag of leads carefully on top.
- Your instructor will check the tray back in.
CONCLUSIONS
Comment on Delay: With respect to delay, if one has specific needs to control delay in all or part of an FPGA, then one should not depend on the implementation tools to handle it without directing them. In order to specify that all or certain parts of the design have upper bounds on delay, constraints can be placed on the synthesis tools. When such delay constrained designs are done, place and route are typically more difficult and, for complex, tightly-constrained circuits, the process can become quite long.
Comment on Schematics: This lab should have vividly demonstrated that what you see is not necessarily what you get, at least when you draw a schematic. Always bear in mind that the FPGA does not have gates that are simply interconnected as you draw them, rather your schematic design must be converted to the resources actually available on the FPGA. In this mapping process, the synthesis tools will attempt to optimize your design. However, if your design is delay-dependent (as the simple project was) and the tools perform their optimization without regard to delay (as they did here); then the optimization can lead to undesired and/or unexpected results. As an engineer, you will need to always be aware of exactly what your tools are doing for you (or to you, as the case may be). (Note that post-implementation simulation did reveal the problem without implementing it.)
As your reward for completing the lab, turn off all traces and the grid on the scope, select Print/Utility and then simultaneously press the second and third buttons from the left below the scope screen.
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K-map for segment ___
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