






Study with the several resources on Docsity
Earn points by helping other students or get them with a premium plan
Prepare for your exams
Study with the several resources on Docsity
Earn points to download
Earn points by helping other students or get them with a premium plan
Community
Ask the community for help and clear up your study doubts
Discover the best universities in your country according to Docsity users
Free resources
Download our free guides on studying techniques, anxiety management strategies, and thesis advice from Docsity tutors
These are the Laboratory of Digital Logic which includes Implementation, Altera Cyclone, Subfunction, Inputs to Outputs, Multiplexers and Pass Transistors, Interconnections, Maximum Expected, Two Circuits, Flip Flop etc. Key important points are: Combinational Logic, Implementation, Altera Cyclone, Subfunction, Inputs to Outputs, Multiplexers and Pass Transistors, Interconnections, Maximum Expected, Two Circuits, Flip Flop
Typology: Lecture notes
1 / 12
This page cannot be seen from the preview
Don't miss anything!
In this experiment, you will design, implement and verify two combinational logic circuits. One circuit implements a very simple logic function and the other implements a BCD-to-7-segment code converter. After performing this experiment, you should be able to:
In the Altera Cyclone technology which we are using, logic functions are decomposed by the implementation tools into 4-input subfunctions. (Even though you are drawing gates in your schematic, what you see is NOT what you get!) Each subfunction is then implemented by a truth table defined by programming the SRAM that defines the FPGA’s functionality. Each of the truth tables has a delay which contributes to the delay down one or more paths from inputs to outputs of the function being implemented. In addition, the connections in the FPGA between the inputs, truth tables, and outputs pass through buffers, multiplexers and pass transistors as determined by the circuit specification and the routing paths determined by the implementation tools.
The decomposition into subfunctions combined with the routing of the interconnections between them yields considerable uncertainty in the propagation delay from input to output of an implemented circuit. A sophisticated user of the tools may use constraints to specify the maximum delays allowable, forcing the tools to attempt to meet or better these delays. Whether or not delays are specified, it is useful to know either whether delay specifications are met or some measure of the delays present. Since most combinational circuits are placed in a sequential environment, there is usually interest in the worst case delay that can occur in the operation of the circuit from any combinational logic input to any combinational logic output (equivalently, in the sequential circuit: from input to output, from input to flip-flop, from flip-flop to flip-flop, and from flip-flop to output). Worst case delay estimates are determined by adding up the maximum expected delays through the combinational circuit including both logic and interconnections. Because of the uncertainty discussed in the previous paragraph, worst case delay can be known only after the implementation process has been completed including the decomposition into subfunctions and the interconnect routing.
In this experiment, we will construct two circuits to be discussed later. With first circuit we will investigate some of
Figure 1 Simple Circuit
The BCD-to-7-segment code converter (commonly referred to as a BCD-to-7-segment decoder) is used to convert a binary coded decimal (BCD) value to the appropriate segment pattern for a 7-segment display. Since BCD values are 4-bit numbers in the range 0-9, how we treat the remaining possible values of 10-15 will impact our design. While we might consider those values to be ‘don’t-cares’, simplifying the logic required compared to making the display blank for those values, for this lab you will design the decoder so that it displays a specific pattern for all non-BCD values. The segments in the display are typically identified in industry by the letters a-g, corresponding to the segments shown below.
f
a b g e c d Figure 2 Seven-Segment Display Convention
So, the input to your circuit will be a 4-bit number (label these signals D3, D2, D1, D0; with D3 being the most significant bit), and there will be 7 outputs (label these signals A, B, C, D, E, F, G to correspond to the segment pattern shown above) that will light the display in the patterns shown below in Figure 3 for all valid inputs. All invalid inputs shall be considered as don’t-care conditions in the logic design.
Figure 3 Seven-Segment Display Patterns
To make our BCD-to-7-segment decoder design easier to use and to easily create multiple instances of it, we will also embed it in a hierarchy block, and then make connections to the block in order to test our design.
Provide answers to the following.
3) CHECKPOINT: Have your instructor observe the waveforms.
First, we will apply inputs to the BCD decoder using the DIP switches and observe the seven segment display to verify the functional correctness of your decoder. First, we will load the bcd_init.sof file into the FPGA.
We now want to evaluate the worst case time delay through the decoder that we observed during timing simulation. Because there are only four input variables and three of them are fixed, this will be greatly simplified. We will use a clock signal to stimulate the input with the longest delay, and the DIP switches to set the other inputs.
Comment on Delay: With respect to delay, if one has specific needs to control delay in all or part of an FPGA, then one should not depend on the implementation tools to handle it without directing them. In order to specify that all or certain parts of the design have upper bounds on delay, constraints can be placed on the synthesis tools. When such delay constrained designs are done, place and route are typically more difficult and, for complex, tightly-constrained circuits, the process can become quite long.
Comment on Schematics: This lab should have vividly demonstrated that what you see is not necessarily what you get, at least when you draw a schematic. Always bear in mind that the FPGA does not have gates that are simply interconnected as you draw them, rather your schematic design must be converted to the resources actually available on the FPGA. In this mapping process, the synthesis tools will attempt to optimize your design. However, if your design is delay-dependent (as the simple project was) and the tools perform their optimization without regard to delay (as they did here); then the optimization can lead to undesired and/or unexpected results. As an engineer, you will need to always be aware of exactly what your tools are doing for you (or to you, as the case may be). (Note that post-implementation simulation did reveal the problem without implementing it.)
As your reward for completing the lab, turn off all traces and the grid on the scope, select Print/Utility and then simultaneously press the second and third buttons from the left below the scope screen.
00 01 11
10
11
01
00
D1 D D3 D
K-map for segment ___
00 01 11 10
10
11
01
00
D1 D D3 D
K-map for segment ___
00 01 11 10
10
11
01
00
D1 D D3 D
K-map for segment ___
00 01 11 10
10
11
01
00
D1 D D3 D