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Problem 1 (25 points) Combinatorial Logic
[10 pts.] a) You are given the Boolean function. Complete the truth
table for. Hint: Simplify.
[8 pts.] b) In this problem you will design a combinational circuit which takes an 8 bit number A[7:0] and cal-
culates. For example, if the input , then. The circuit is built from 1 bit modules as shown below.
Complete the truth table for the module:
[2 pts.] c) Draw a logic diagram for functions and Borrow Out.
[5 pts.] d) Show how the 1-bit modules would be interconnected to create an 8-bit subtract 1 circuit.
A Borrow In Y Borrow Out
0 0 0 1 1 0 1 1
f ( A B C , , ) = ( ABC โ
BC ) ( A โ
C โ
AB ) f ( A B C , , ) f ( A B C , , )
A B C
0 0 0 0 0 1 0 1 0 0 1 1
f ( A B C , , ) A B C
1 0 0 1 0 1 1 1 0 1 1 1
f ( A B C , , )
Y = A โ 1 A = 000011002 Y = 000010112
Y
Yn An
BI BO
A
(1 bit module)
Borrow In (^) Borrow Out
Y
Problem 2 (25 points) Timing
Complete the time diagram for the figure below, assuming unit delays for all gates and inverters (transport delay only), and no delay in the wires. (The dashed lines in the diagram represent missing sections of the timing dia- gram.) Complete the table below with the voltage levels at the specified location in the timing diagram, i.e., L for low and H for high. Example: At location 0, the appropriate voltage level is H. (This problem will be graded + 1 for correct, 0 for blank, and โ1 for incorrect, with minimum score of 0 points.)
1 _____ 6 _____ 11 _____ 16 _____ 21 _____ 2 _____ 7 _____ 12 _____ 17 _____ 22_____ 3 _____ 8 _____ 13 _____ 18 โโโโโ 23_____ 4 _____ 9 _____ 14 _____ 19 โโโโโ 24 _____ 5 _____ 10 _____ 15 _____ 20 โโโโโ 25 _____
C
A
B
D
E
Q 1
Q 2
Q 1
Q 2
A
B
C
D
E
25
1718
24
11
19 20 21 22 23
12 13 14
6 7
0 1 2 3 4 5
(^8910)
15 16
Problem 4 (20 points)
Design a Mealey FSM with synchronized input X.H and output Y.H. The output Y should be asserted for one clock cycle whenever the sequence ..011 or ..100 has been input on X. Note that patterns may be overlapping, e.g., X = ..0000111000.. generates Y = ..000001001... (The patterns may also overlap themselves.) The machine should start assuming that a โ0โ has already been input.
[12 pts.] a) Complete the state diagram for the sequence detector:
[8 pts.] b) Complete the state table for the FSM.
Input X.H
Current State (^) Next State Output Y.H
0 1
S 0
0 1
S 1
0 1
S 2
0 1
S 3
S 0
S 3
S 1
S 2
Q 1 Q 0 Q 1 Q 0
Problem 5 (10 points)
What is the minimum clock period for proper operation for this shift register circuit?
minimum clock period
Data: hold time
setup time
propagation delay through FF
ns
t hold =6ns
t setup =20ns
8ns < t cko <12ns
D Q
Q 0
D Q
Q 1
Clock
Clock
Q 0
Q 1
10ns delay
