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This course focuses on quantitative principle of computer design, instruction set architectures, datapath and control, memory hierarchy design, main memory, cache, hard drives, multiprocessor architectures, storage and I/O systems, computer clusters. This lecture includes: code, Fragment, Speculation, Register, Code, Instructions, Branch, Exeptions, Poison, If, Then, Else
Typology: Slides
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LD R1,0(R3) ;load A LD R14,0(R2) ;speculative load B BEQZ R1,L3 ;other branch of if DADDUI R14,R1,#4 ;else clause
L3: SD R14,0(R3) ;non-speculative store
L2: SD R1,0(R3) ;store A
Method 2: Speculative Instructions
This approach introduces speculative version of instructions, such as
These instructions are used to preserve exception behavior exactly rather than speculatively
Method 2: Speculative Instructions These instructions
Don’t generate terminating exception; rather these instructions check for such exceptions The combined used of two or more speculative instructions, such as sLD and SPECCK, preserve the exception behavior exactly
Revised code using speculative instructions
LD R1,0(R3) ;load A sLD R14,0(R2) ;speculative, no termination BNEZ R1, L1 ;test A SPECCK 0(R2) ;speculative check J L2 ;skip else L1: DADDUI R1,R1,#4 ;else clause L2: SD R1,0(R3) ;store A
Speculate Branch taken/not-taken (in this example Not-Taken) and save value B at 0(R2) in temporary register R14; i.e., the basic block for THEN (in this case the value B) is maintained
Check if the speculation is correct or not, i.e., Branch has taken or otherwise
Here, the load instruction speculate in respect of the branch instruction whether it will be taken or not-taken
The speculation check requires to maintain a basic block for THEN clause, thus preserve the exception behavior
Notice that extra code is required to check for possible exception – thus, result in overhead
Method 3: Poison Bit
Here, a set of bits called “poison - bits” is attached to every instruction and to every result register to indicate whether the instruction is speculative
These bits are used to track exceptions as they occur; but postpones any terminating exception until a value is actually used
Method 3: Poison Bit
Sequence of steps to preserve exception behavior using poison bits
Let us once again consider our earlier example and:
See how it would be compiled with speculative instructions SLD and register R14 with poison-bit; and Show where an exception for the speculative memory reference would be recognized
Assume A is at 0(R3) and B is at 0(R2); and that R14 is unused and available
Note here, If the speculative sLD generates a terminating exception, the poison bit of the R14 will be turned on
When the non-speculative SW instruction occurs, it will raise an exception if the poison bit for R14 is turned on