ABES Institute of Technology
Ghaziabad
Affiliated to Dr. A.P.J. AKTU, Lucknow
LAB MANUAL
Department of Computer Science & Engineering
Subject Name: Computer Organization Lab
Subject Code: KCS-352
Session: 2020-21
Semester: 3rd
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Coa lab manual for semester 3 btech, Lab Reports of Computer Fundamentals
Computer organization and Architecture lab manual for Btech Semester 3. It contains total 9 experiments with complete diagrams.
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2020/2021
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ABES Institute of Technology
Ghaziabad
Affiliated to Dr. A.P.J. AKTU, Lucknow
LAB MANUAL
Department of Computer Science & Engineering
Subject Name: Computer Organization Lab
Subject Code: KCS-
Session: 2020-
Semester: 3
rd
INDEX ABES Institute of Technology, Ghaziabad Department of Computer Science & Engineering
Institute Vision
To be leading institution in technical education providing education
and training enabling human resource to serve nation and world at
par with global standards in education
S.N o Contents
1. Vision & Mission of the Institute & Department /PO-PSO
2. Prescribed University Syllabus
3. List of Experiments/ LAB Plan
4. Course Outcome
5. CO-PO-PSO Mapping
6. Lab Manuals
7. FAQ
Department
Mission
1) Provide quality education in the field of computer science and
engineering through experienced and qualified faculty members.
2) Motivate learners for higher studies and research oriented activities
by utilizing resources of Centers of Excellence.
3) Inculcate societal values, professional ethics, team work, and
leadership qualities by having exposure at National and International
level activities.
ABES Institute of Technology, Ghaziabad
Program Educational Objectives (PEOs)
PEO
Graduates of the program are expected to be employed in IT industry or Indulge in higher studies and research. PEO Graduates of the program are expected to exhibit curiosity to learn new technologies and work with ethical values and team work. PEO Graduates of the program are expected to design and develop innovative solutions related to real world problems of the society.
Program Specific Outcomes (PSOs)
PSO 1 Solve complex problems using data structures and other advanced suitable algorithms. PSO 2 Interpret fundamental concepts of computer systems and understand its hardware and software aspect. PSO 3 Analyze the constraints of the existing data base management systems and get experience on large-scale analytical methods in the evolving technologies. Department of Computer Science & Engineering
PSO 4
Develop intelligent systems and implement solutions to cater the business specific requirements.
Program Outcomes (POs)
PO1 Engineering knowledge PO2 Problem analysis PO3 Design/development of solutions PO4 Conduct investigations of complex problems PO5 Modern tool usage PO6 The engineer and society PO7 Environment and sustainability PO8 Ethics PO9 Individual and team work PO10 Communication PO11 Project management and finance PO12 Life-long learning
OBSERVATION TABLE:
HALF ADDER:
INPUTS OUTPUT
A B S C
FULL ADDER:
INPUTS OUTPUTS
A B C S CARRY
RESULT: The Half Adder & Full Adder circuits are verified. PRECAUTIONS :
- Make the connections according to the IC pin diagram.
- The connections should be tight.
- The Vcc and ground should be applied carefully at the specified pin only. VIVA QUESTIONS
1. Give the basic rules for binary addition? 0+0 = 0; 0+1 = 1; 1+1 = 1 0; 1+0 = 1. 2. Specify the no. of I/P and O/P of Half adder? Two inputs & one output. 3. What is the drawback of half adder? We can’t add carry bit from previous stage. 4. Write the equation for sum & carry of half adder? Sum = A XOR B; carry = A.B. 5. Write the equation for sum & carry of full adder? SUM= A’B’C+A’BC’+AB’C’+ABC; CARRY=AB+BC+AC.
EXPERIMENT NO. 2
AIM: Implementing Binary -to -Gray, Gray -to -Binary code conversions. APPARATUS REQUIRED : Digital board DB06, DC Power Supply +5 V from external source or ST2611 Digital lab, Digital Multimeter or Digital Lab ST2611. BRIEF THEORY : The availability of a large variety of codes for the same discrete elements of information results in the use of different codes by different digital system. It is sometimes necessary to use the output of one system as the input to another. A conversion circuit must be inserted between the two systems if each uses different codes for the same information. Thus, a code converter is a circuit that makes the two systems compatible even though each uses a different binary code. Logic diagram & Truth Table : (Logic 1 = +5V & Logic 0= GND) Binary to Gray Code Gray to Binary Code
EXPERIMENT NO. 3
AIM: Implementing 3-8 line DECODER and Implementing 4x1 and 8x1 MULTIPLEXERS. APPARATUSREQUIRED :Power Supply, Digital Trainer, Connecting Leads, IC’s74153(4x1 multiplexer). BRIEF THEORY : MULTIPLEXER: Multiplexer generally means many into one. A multiplexer is acircuit with many Inputs but only one output. By applying control signals we can steer any input to the output .The fig. (1) Shows the general idea. The ckt. has n-input signal, control signal & one output signal. Where 2n^ = m. One of the popular multiplexer is the 16 to 1 multiplexer, which has 16 input bits, 4 control bits & 1 output bit. PIN CONFIGURATION : IC 74153 (4x1 multiplexer) (4x8 multiplexer)
PIN NAMES
S0–S2 Select Inputs E Enable (Active LOW) Input I0–I7 Multiplexer Inputs Z Multiplexer Output (Note b) Z’ Complementary Multiplexer Output LOGIC DIAGRAM: Multiplexer (4x1) IC 74153
Truth Table of multiplexer (8x1) IC 74153 PROCEDURE :
- Fix the IC's on the bread board &give the input supply.
- Make connection according to the circuit.
- Give select signal and strobe signal at respective pins.
- Connect +5 V Vcc supply at pin no 24 & GND at pin no 12.
- Verify the truth table for various inputs. RESULT : Verify the truth table of multiplexer for various inputs. 3-8 LINE DECODER BRIEF THEORY : 3-8 LINE DECODER is designed to be used in high-performance memory-decoding or data- routing applications requiring very short propagation delay times. In high-performance memory systems, this decoder can be used to minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay times of this decoder and the enable time of the memory are usually less than the typical access time of the memory. This means that the effective system delay introduced by the decoder is negligible. The conditions at the binary-select (A, B, C) inputs and the three enable (G1, G2A, G2B) inputs select one of eight output lines. Two active-low and one active-high enable inputs reduce the need for external gates
or inverters when expanding. A 24-line decoder can be implemented without external inverters and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications. PIN CONFIGURATION : OBSERVATION TABLE :
3) The Vcc and ground should be applied carefully at the specified pin only. VIVA QUESTIONS
1. Why is MUX called as “Data Selector”? This selects one out of many inputs. 2. What do you mean by Multiplexing? Multiplexing means selecting only a single input out of many inputs 3. What is Digital Multiplexer? This multiplexer acts on digital data. 4. What is the function of Enable input to any IC? When this enable signal is activated. 5. What is demultiplexer? A demultiplexer transmits the data from a single source to various sources.
EXPERIMENT NO. 4
AIM : Verify the excitation tables of various Flip-Flops. APPARATUS REQUIRED: IC’ S 7400, 7402 Digital Trainer & Connectingleads. BRIEF THEORY :
- RS FLIP-FLOP: There are two inputs to the flip-flop defined as R and S. WhenI/Ps R = 0 and S = 0 then O/P remains unchanged. When I/Ps R = 0 and S = 1 the flip-flop is switches to the stable state where O/P is 1 i.e. SET. The I/P condition is R = 1 and S = 0 the flip-flop is switched to the stable state where O/P is 0 i.e. RESET. The I/P condition is R = 1 and S = 1 the flip-flop is switched to the stable state where O/P is forbidden.
- JK FLIP-FLOP :For purpose of counting, the JK flip-flop is the idealelement to use. The variable J and K are called control I/Ps because they determine what the flip- flop does when a positive edge arrives. When J and K are both 0s, both AND gates are disabled and Q retains its last value.
- D FLIP –FLOP : This kind of flip flop prevents the value of D fromreaching the Q output until clock pulses occur. When the clock is low, both AND gates are disabled D can change value without affecting the value of Q. On the other hand, when the clock is high, both AND gates are enabled. In this case, Q is forced to equal the value of D. When the clock again goes low, Q retains or stores the last value of D. a D flip flop is a bistable circuit whose D input is transferred to the output after a clock pulse is received.
- T FLIP-FLOP : The T or "toggle" flip-flop changes its output on each clock edge, giving an output which is half the frequency of the signal to the T input. It is useful for constructing binary counters, frequency dividers, and general binary addition devices. It can be made from a J-K flip-flop by tying both of its inputs high. CIRCUIT DIAGRAM : SR Flip Flop D Flip Flop
RESULT : Truth table is verified on digital trainer. PRECAUTIONS :
- Make the connections according to the IC pin diagram.
- The connections should be tight.
- The Vcc and ground should be applied carefully at the specified pin only. VIVA QUESTIONS 1. Flip flop is Astable or Bistable? Bistable. 2. What is the I/Ps of JK flip–flop where this race round condition occurs? Both the inputs are 1. 3. When RS flip-flop is said to be in a SET state? When the output is 1. 4. When RS flip-flop is said to be in a RESET state? When the output is 0. 5. What is the truth table of JK flip-flop? J K Qn+ 0 0 Qn 0 1 0 1 0 1 1 1 Qn, ’
EXPERIMENT NO. 5
AIM : Design of an 8-bit Input/ Output system with four 8-bit Internal Registers. BRIEF THEORY : A universal shift register is an integrated logic circuit that can transfer data in three different modes. Like a parallel register it can load and transmit data in parallel. Like shift registers it can load and transmit data in serial fashions, through left shifts or right shifts. In addition, the universal shift register can combine the capabilities of both parallel and shift registers to accomplish tasks that neither basic type of register can perform on its own. For instance, on a particular job a universal register can load data in series (e.g. through a sequence of left shifts) and then transmit/output data in parallel. Universal shift registers, as all other types of registers, are used in computers as memory elements. Although other types of memory devices are used for the efficient storage of very large volume of data, from a digital system perspective when we say computer memory we mean registers. In fact, all the operations in a digital system are performed on registers. Examples of such operations include multiplication, division, and data transfer. In order for the universal shift register to operate in a specific mode, it must first select the mode. To accomplish mode selection the universal register uses a set of two selector switches, S1 and S0. Operating Mode S1 S Locked 0 0 Shift-Right 0 1 Shift-Left 1 0 Parallel Loading 1 1