CENTRAL PROCESSING UNIT
• Introduction
• General Register Organization
• Stack Organization
• Instruction Formats
• Addressing Modes
• Data Transfer and Manipulation
• Program Control
• Reduced Instruction Set Computer
Docsity.com
Prepare for your exams
Study with the several resources on Docsity
Earn points to download
Earn points by helping other students or get them with a premium plan
Guidelines and tips
Prepare for your exams
Study with the several resources on Docsity
Earn points to download
Earn points by helping other students or get them with a premium plan
Community
Ask the community
Ask the community for help and clear up your study doubts
University Rankings
Discover the best universities in your country according to Docsity users
Free resources
Our save-the-student-ebooks!
Download our free guides on studying techniques, anxiety management strategies, and thesis advice from Docsity tutors
Central Processing Unit - Computer Architecture - Lecture Slides, Slides of Computer Architecture and Organization
Central Processing unit, General Register Organization, Stack Organization, Instruction Formats, Addressing Modes, Data Transfer and Manipulation, Program Control are topics professor discussed in class.
Typology: Slides
2011/2012
1 / 61
This page cannot be seen from the preview
Don't miss anything!
Related documents
Partial preview of the text
Download Central Processing Unit - Computer Architecture - Lecture Slides and more Slides Computer Architecture and Organization in PDF only on Docsity!
CENTRAL PROCESSING UNIT
- Introduction
- General Register Organization
- Stack Organization
- Instruction Formats
- Addressing Modes
- Data Transfer and Manipulation
- Program Control
- Reduced Instruction Set Computer
MAJOR COMPONENTS OF CPU
Introduction
- Storage Components
Registers Flags
- Execution (Processing) Components
Arithmetic Logic Unit(ALU) Arithmetic calculations, Logical computations, Shifts/Rotates
- Transfer Components
Bus
- Control Components
Control Unit RegisterFile ALU
Control Unit
GENERAL REGISTER ORGANIZATION
General Register Organization
SELA { MUX MUX } SELB
OPR^ ALU
R R R R R R R
Input
3 x 8 decoder
SELD
Load (7 lines)
Output
A bus B bus
Clock
OPERATION OF CONTROL UNIT
The control unit
Directs the information flow through ALU by
- Selecting various Components in the system
- Selecting the Function of ALU
Example: R1 R2 + R [1] MUX A selector (SELA): BUS A R [2] MUX B selector (SELB): BUS B R [3] ALU operation selector (OPR): ALU to ADD [4] Decoder destination selector (SELD): R1 Out Bus
Control Word
Encoding of register selection fields
Control
Binary Code SELA SELB SELD 000 Input Input None 001 R1 R1 R 010 R2 R2 R 011 R3 R3 R 100 R4 R4 R 101 R5 R5 R 110 R6 R6 R 111 R7 R7 R
SELA SELB SELD OPR
3 3 3 5
REGISTER STACK ORGANIZATION
Register Stack
Push, Pop operations
/* Initially, SP = 0, EMPTY = 1, FULL = 0 */ PUSH POP
Stack Organization
SP SP + 1 DR M[SP] M[SP] DR SP SP 1 If (SP = 0) then (FULL 1) If (SP = 0) then (EMPTY 1) EMPTY 0 FULL 0
Stack
- Very useful feature for nested subroutines, nested interrupt services
- Also efficient for arithmetic expression evaluation
- Storage which can be accessed in LIFO
- Pointer: SP
- Only PUSH and POP operations are applicable
A
B
C
0
1
2
3
4
63
Address
FULL EMPTY
SP
DR
Flags
Stack pointer
stack
6 bits
MEMORY STACK ORGANIZATION
Stack Organization
- A portion of memory is used as a stack with a processor register as a stack pointer
- PUSH: SP SP - 1
M[SP] DR
- POP: DR M[SP]
SP SP + 1
Memory with Program, Data, and Stack Segments
4001
4000
3999
3998
3997
3000
Data (operands)
Program (instructions)
1000 PC
AR
SP stack
Stack grows In this direction
- Most computers do not provide hardware to check stack overflow (full stack) or underflow (empty stack) must be done in software
PROCESSOR ORGANIZATION
- In general, most processors are organized in one of 3 ways
- Single register (Accumulator) organization » Basic Computer is a good example » Accumulator is the only general purpose register
- General register organization » Used by most modern computer processors » Any of the registers can be used as the source or destination for computer operations
- Stack organization » All operations are done using the hardware stack » For example, an OR instruction will pop the two top elements from the stack, do a logical OR on them, and push the result on the stack
INSTRUCTION FORMAT
OP-code field - specifies the operation to be performed Address field - designates memory address(es) or a processor register(s) Mode field - determines how the address field is to be interpreted (to get effective address or the operand)
- The number of address fields in the instruction format
depends on the internal organization of CPU
- The three most common CPU organizations:
Instruction Format
Single accumulator organization: ADD X /* AC AC + M[X] / General register organization: ADD R1, R2, R3 / R1 R2 + R3 / ADD R1, R2 / R1 R1 + R2 / MOV R1, R2 / R1 R2 / ADD R1, X / R1 R1 + M[X] / Stack organization: PUSH X / TOS M[X] */ ADD
- Instruction Fields
ONE, AND ZERO-ADDRESS INSTRUCTIONS
- One-Address Instructions
- Use an implied AC register for all data manipulation
- Program to evaluate X = (A + B) * (C + D) :
Instruction Format
LOAD A /* AC M[A] */
ADD B /* AC AC + M[B] */
STORE T /* M[T] AC */
LOAD C /* AC M[C] */
ADD D /* AC AC + M[D] */
MUL T /* AC AC * M[T] */
STORE X /* M[X] AC */
- Zero-Address Instructions
- Can be found in a stack-organized computer
- Program to evaluate X = (A + B) * (C + D) :
PUSH A /* TOS A / PUSH B / TOS B / ADD / TOS (A + B) / PUSH C / TOS C / PUSH D / TOS D / ADD / TOS (C + D) / MUL / TOS (C + D) * (A + B) */ Docsity.com
ADDRESSING MODES
Addressing Modes
- Addressing Modes
Specifies a rule for interpreting or modifying the address field of the instruction (before the operand is actually referenced)
Variety of addressing modes
- to give programming flexibility to the user
- to use the bits in the address field of the instruction efficiently
TYPES OF ADDRESSING MODES
- Register Mode Address specified in the instruction is the register address - Designated operand need to be in a register - Shorter address than the memory address - Saving address field in the instruction - Faster to acquire an operand than the memory addressing - EA = IR(R) (IR(R): Register field of IR)
- Register Indirect Mode Instruction specifies a register which contains the memory address of the operand
- Saving instruction bits since register address is shorter than the memory address
- Slower to acquire an operand than both the register addressing or memory addressing
- EA = [IR(R)] ([x]: Content of x)
- Autoincrement or Autodecrement Mode
- When the address in the register is used to access memory, the value in the register is incremented or decremented by 1 automatically
Addressing Modes
TYPES OF ADDRESSING MODES
Addressing Modes
- Direct Address Mode Instruction specifies the memory address which can be used directly to access the memory
- Faster than the other memory addressing modes
- Too many bits are needed to specify the address for a large physical memory space
- EA = IR(addr) (IR(addr): address field of IR)
- Indirect Addressing Mode The address field of an instruction specifies the address of a memory location that contains the address of the operand
- When the abbreviated address is used large physical memory can be addressed with a relatively small number of bits
- Slow to acquire an operand because of an additional memory access
- EA = M[IR(address)]
ADDRESSING MODES - EXAMPLES -
Addressing Mode
Effective Address
Content of AC
Addressing Modes
Direct address 500 /* AC (500) / 800 Immediate operand - / AC 500 / 500 Indirect address 800 / AC ((500)) / 300 Relative address 702 / AC (PC+500) / 325 Indexed address 600 / AC (RX+500) / 900 Register - / AC R1 / 400 Register indirect 400 / AC (R1) / 700 Autoincrement 400 / AC (R1)+ / 700 Autodecrement 399 / AC -(R) */ 450
Load to AC Mode Address = 500 Next instruction
200 201 202
399 400
450 700
500 800
600 900
702 325
800 300
Address Memory
PC = 200
R1 = 400
XR = 100
AC
DATA TRANSFER INSTRUCTIONS
Load LD Store ST Move MOV Exchange XCH Input IN Output OUT Push PUSH Pop POP
Name Mnemonic
- Typical Data Transfer Instructions
Direct address LD ADR AC M[ADR] Indirect address LD @ADR AC M[M[ADR]] Relative address LD $ADR AC M[PC + ADR] Immediate operand LD #NBR AC NBR Index addressing LD ADR(X) AC M[ADR + XR] Register LD R1 AC R Register indirect LD (R1) AC M[R1] Autoincrement LD (R1)+ AC M[R1], R1 R1 + 1 Autodecrement LD -(R1) R1 R1 - 1, AC M[R1]
Mode Assembly Convention Register Transfer
Data Transfer and Manipulation
- Data Transfer Instructions with Different Addressing Modes