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Central Processing unit, General Register Organization, Stack Organization, Instruction Formats, Addressing Modes, Data Transfer and Manipulation, Program Control are topics professor discussed in class.
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Introduction
Registers Flags
Arithmetic Logic Unit(ALU) Arithmetic calculations, Logical computations, Shifts/Rotates
Bus
Control Unit RegisterFile ALU
Control Unit
General Register Organization
R R R R R R R
Input
3 x 8 decoder
SELD
Load (7 lines)
Output
A bus B bus
Clock
The control unit
Directs the information flow through ALU by
Example: R1 R2 + R [1] MUX A selector (SELA): BUS A R [2] MUX B selector (SELB): BUS B R [3] ALU operation selector (OPR): ALU to ADD [4] Decoder destination selector (SELD): R1 Out Bus
Control Word
Encoding of register selection fields
Control
Binary Code SELA SELB SELD 000 Input Input None 001 R1 R1 R 010 R2 R2 R 011 R3 R3 R 100 R4 R4 R 101 R5 R5 R 110 R6 R6 R 111 R7 R7 R
SELA SELB SELD OPR
3 3 3 5
Register Stack
Push, Pop operations
/* Initially, SP = 0, EMPTY = 1, FULL = 0 */ PUSH POP
Stack Organization
SP SP + 1 DR M[SP] M[SP] DR SP SP 1 If (SP = 0) then (FULL 1) If (SP = 0) then (EMPTY 1) EMPTY 0 FULL 0
Stack
A
B
C
0
1
2
3
4
63
Address
FULL EMPTY
SP
DR
Flags
Stack pointer
stack
6 bits
Stack Organization
Memory with Program, Data, and Stack Segments
4001
4000
3999
3998
3997
3000
Data (operands)
Program (instructions)
1000 PC
AR
SP stack
Stack grows In this direction
OP-code field - specifies the operation to be performed Address field - designates memory address(es) or a processor register(s) Mode field - determines how the address field is to be interpreted (to get effective address or the operand)
Instruction Format
Single accumulator organization: ADD X /* AC AC + M[X] / General register organization: ADD R1, R2, R3 / R1 R2 + R3 / ADD R1, R2 / R1 R1 + R2 / MOV R1, R2 / R1 R2 / ADD R1, X / R1 R1 + M[X] / Stack organization: PUSH X / TOS M[X] */ ADD
Instruction Format
PUSH A /* TOS A / PUSH B / TOS B / ADD / TOS (A + B) / PUSH C / TOS C / PUSH D / TOS D / ADD / TOS (C + D) / MUL / TOS (C + D) * (A + B) */ Docsity.com
Addressing Modes
Specifies a rule for interpreting or modifying the address field of the instruction (before the operand is actually referenced)
Variety of addressing modes
Addressing Modes
Addressing Modes
Addressing Mode
Effective Address
Content of AC
Addressing Modes
Direct address 500 /* AC (500) / 800 Immediate operand - / AC 500 / 500 Indirect address 800 / AC ((500)) / 300 Relative address 702 / AC (PC+500) / 325 Indexed address 600 / AC (RX+500) / 900 Register - / AC R1 / 400 Register indirect 400 / AC (R1) / 700 Autoincrement 400 / AC (R1)+ / 700 Autodecrement 399 / AC -(R) */ 450
Load to AC Mode Address = 500 Next instruction
200 201 202
399 400
450 700
500 800
600 900
702 325
800 300
Address Memory
PC = 200
R1 = 400
XR = 100
AC
Load LD Store ST Move MOV Exchange XCH Input IN Output OUT Push PUSH Pop POP
Name Mnemonic
Direct address LD ADR AC M[ADR] Indirect address LD @ADR AC M[M[ADR]] Relative address LD $ADR AC M[PC + ADR] Immediate operand LD #NBR AC NBR Index addressing LD ADR(X) AC M[ADR + XR] Register LD R1 AC R Register indirect LD (R1) AC M[R1] Autoincrement LD (R1)+ AC M[R1], R1 R1 + 1 Autodecrement LD -(R1) R1 R1 - 1, AC M[R1]
Mode Assembly Convention Register Transfer
Data Transfer and Manipulation