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The steps to design a 3-bit gray code counter using sequential logic. The process includes deriving a circuit state diagram, creating a state table, choosing flip-flops, creating a circuit excitation table, generating k-maps, and obtaining minimized sop equations. The document also covers the differences between mealy and moore models in sequential logic.
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C. E. Stroud
Sequential Logic Design (11/03)
C. E. Stroud
Sequential Logic Design (11/03)
1
1
1
1
1 1
1 R=0R=
0 (^00) 0
0
Next state(X Y Z)
Current state
Inputs
State order:
0
C. E. Stroud
Sequential Logic Design (11/03)
-^
Jx =Jx
Kx = R’ + Y’Z’
Dy =Dy
SzSz = RXY + RX
Rz = R’ + XY’ + X’Y
C. E. Stroud
Sequential Logic Design (11/03)
5
Jx
Kx Clk Sz
Dy Rz Clk
Clk
C. E. Stroud
Sequential Logic Design (11/03)
Mealy & Moore State Diagrams
¾
Outputs associatedwith state transition ¾
Output valuesshown with inputs
¾
Outputs associatedwith states only ¾
Output valuesshown with states
Input
/ Output
StateorderXY States/ Output
C. E. Stroud
Sequential Logic Design (11/03)
8
Mealy
Moore
X
C. E. Stroud
Sequential Logic Design (11/03)
10
Mealy & Moore Design Examples
X^
Y^
Mealy
Moore
X X
Y X Y
In
Y Y
X X Y
X X
Y X Y
In
Y Y
X X Y X^ Y
OMoore
Y X
OMealy
Mealy
Moore
Clk
Clk
