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Module-IX
Lecture-I
Introduction to Automatic Test Pattern Generation (ATPG)
and ATPG Algebras
1. Introduction
In the last module we saw that in a circuit some faults are “easy to test” and some others are “difficult to test”. Further, we have also seen an algorithm that can estimate the “easy to test faults” and the ones that are “difficult to test”. Fault simulation algorithms are used to determine test patters for easy to test faults and for the others, sensitization– propagation -justification approach is used. In the last module we also discussed in detail, most of the commonly used fault simulation algorithms. In this module we will study automatic test pattern generation (ATPG) using sensitization–propagation -justification approach. We will first introduce the basics of ATPG and ATPG algebras. Following that in the next lecture of the module we will present D-algorithm--the basic and first ATPG algorithm developed. Also, we will present basics of some other advanced ATPG algorithms, which were successors of the D-algorithm.
2. What is ATPG
ATPG stands for automatic test pattern generation. As the name suggests, ATPG procedure involves generation of input patterns that can ascertain presence or absence of fault(s) at some location(s) in a circuit. There are several ways of ATPG. In the last module we have seen two of them- (i) fault simulation and (ii) sensitization–propagation –justification. These techniques are based on Boolean logic manipulations and are most widely used. However, it must not be felt that only logic based schemes can be used for ATPG. Here we briefly discuss another interesting ATPG technique that requires thermal imaging technique [1]. Thermal imaging technique involves taking images of the silicon
(of the circuit) and then drawing conclusions based on temperature profile of various regions of the silicon. In case of ATPG based on imaging technique, one needs to find an input pattern that results in difference of temperature at a location (which is being tested) with and without fault. For example, when a net say A, has stuck-at-0 fault and primary inputs are applied such that net A gets 1, then temperature in A will be abnormally higher, due to high short circuit current. The advantage is, we need not have to worry about propagating the effect of the fault to primary outputs, as all internal points are observable in terms of temperature profile. So, sensitization is enough to generate a test pattern. However, the instrumentation cost for thermal imaging is high. So, widely used ATPG algorithms are based on logic manipulations. Henceforth, when we talk about ATPG it will imply techniques based on logic operations. Next we will see basics of ATPG algebra, which will be required to understand D-algorithm.
- ATPG algebra As we all know, Boolean algebra comprising of 0 and 1, is used for studying behavior of digital circuits. However, if we consider circuits with fault, then Boolean algebra will not suffice to represent signal values. Let us take an example. Consider the AND gates given in Figure 1. In order to represent that I1=1,I2=1 detects s-a-0 fault at the output, we need to mark O1 as 1/0-indcating that under normal condition O1 is 1 and under fault it is 0. Similarly, in case of Figure 1(b) we need to mark O1 as 0/1--indicating that under normal condition O1 is 0 and under fault it is 1. So we can see that a single bit (0 or 1) is not enough for representing and studying circuits with fault. I I2 G1 O1 (s-a-1)
0 0
I1 0/1 (Normal: 0, Fault: 1) I2 G1 O1 (s-a-0)
1 1
1/0 (Normal: 1, Fault: 0)
(a) 1/0 is required to representthe detection of fault (b) 0/1 is required to representthe detection of fault
Figure 1. Requirement of more than Boolean (0/1) algebra for studying fault behaviors
Logical operations using Roth’s 5-valued algebra is very similar to Boolean algebra, only we need two Boolean operations when D or is one of the inputs. Some examples are as
follows 1 AND D = D; 1 AND 1/0 involves two computations—(i) 1 AND 1=1, (ii) 1 AND 0=0. 0 OR = ; 0 OR 0/1 involves two computations—(i) 0 OR 0=0, (ii) 0 OR 1=1. =D; NOT(0/1) involves two computations—(i) NOT(0)=1, (ii) NOT(1)=0. When one input is X in logical operation then output is also X, if others inputs are non controlling; else output is determined by the controlling input. Some examples are given below X AND 1 =X; 1 is non controlling in AND logic X AND 0 =0; 0 is controlling in AND logic
- Types of ATPG algorithms 4.1 Exhaustive Testing by “exhaustive” technique implies applying all input combinations and checking for “functional” correctness. As already discussed in last module, for an n- input circuit, an exhaustive test technique would require input combinations. Considering the time required for exhaustive testing, it is infeasible for circuits with more than about 15 inputs. So exhaustive testing techniques are not used in ATPG.
4.2 Random As elaborated in the last module, random ATPG basically involves three steps: Generate a random pattern Determine how many faults are detected by the random pattern (fault simulation) Continue the above two steps till no (or few) new faults are detected by the random pattern. Random patterns can detect “easy to test faults” and the algorithm being fast, it is applied at initial phases of ATPG. Also discussed before, heart of ATPG by random patterns are fault simulation algorithms. We saw four major fault simulations algorithms in the last module namely, sequential, parallel, concurrent and deductive. However, for the faults which cannot be detected by random patterns, we need deterministic ARPG techniques. Now we will see two such types of algorithms (i) symbolic difference and (ii) path sensitization.
4.3 Symbolic Difference ATPG by symbolic difference is basically based on well-known Shannon’s expansion theorem. Let us explain this by an example. Consider an arbitrary Boolean function as f ( x 1 (^) , x 2 ,.. xn ). By Shannon’s expansion rule, the function can be expanded about any variable x 1 say, as f ( x 1 (^) , x 2 ,.. xn )= x 1 (^). f (0, x 2 (^) ,.. xn ) x 1 (^). f (1, x 2 ,.. xn ).
Similarly, for detecting s-a-1 fault at location F, we need
- g f (^) F ( I 1 (^) , I 2 ,.. In ) 0
2. j ,1 j m ^ fg^ j fi (1, I 1 , I 2 ,.. In ) fi (0, I 1 , I 2 ,.. In ) 1
Unfortunately, due to high complexity the Boolean difference is not an efficient way to compute test patterns for large circuits.
4.4 Path sensitization As discussed in the last module, ATPG by path sensitization method is generally applied for “difficult to test faults” and comprises three phases.
- Fault sensitization: In this step a stuck-at fault is activated by setting the signal driving the faulty net to an opposite value from the fault value.
- Fault propagation : In this step a path is selected from the fault site to some primary output, where the effect of the fault can be observed for its detection.
- Line justification : In this step the signals in (internal) nets or some primary inputs, which were assigned for fault sensitization/propagation, are justified by setting (remaining) primary inputs of the circuit. In the second and third steps, a conflict may occur, where a necessary signal assignment contradicts some previously-made assignment. When conflicts occur we need to take a new alternative path for fault propagation and see if all signals can be justified. We have seen some simple examples for ATPG using the path sensitization (sensitization-propagation-justification) approach in the last module. Now we will see a bit more complex example of ATPG using the path sensitization approach. However, instead of using Boolean algebra (as in last module), we will use Roth’s 5 valued algebra. Following that, in the next lecture we will learn D-algorithm--the primary and formal algorithm for ATPG using path sensitization. As shown in Figure 4 (a), there is a s-a-0 fault in input b. To sensitize the fault, simply b is to be made 1. Now let us take the path “ e-f-g-h ” for propagating the effect to the output h. The signals in the nets of the path, in terms of Roth’s 5 valued algebra, are shown in Figure 4(a). It may be noted that we have successfully
propagated D to the output; it implies that the fault can be propagated to the output using the path selected. Now let us justify the signals, by setting the inputs of the gates in the path selected (for fault propagation), but not themselves being in the path, to non-controlling values. For example, net j , is a input to the OR gate that is in the path selected for fault propagation, but j is not itself in the path; so j is to be 0. Similarly, d is to be 1, and a is to be 1. However, it must be noted that j cannot be made 0; if c =1 then j =D and if c =0 then j =1. So we have reached a conflict at j; Figure 4(b). Now we must backtrack and select a new path for propagation.
a
b =
c d
e
f
g (^) h s-a-0 i j
D
D
D
D
(a) Sensitization by b = Propagation by path e-f-g-h a
b =
c d =
e
f
g (^) h s-a-0 i j
D
D
D
D
(b) Justification j= j= D , if c=1 and j=1 if c= (conflict at j)
D 0
Figure 4. Illustration of backtrack in path sensitization based ATPG
5. Conclusions In this lecture we have discussed the basic types of ATPG algorithms and a new 5 valued algebra required in all the major ATPG algorithms (based on path sensitization). In the next lecture we will study in detail the D-algorithm, which is the basis of all path sensitization based ATPG algorithms. As a point of motivation, it must be stated that most of the modern and widely accepted “deterministic” ATPG algorithms are based on path sensitization approach and roots drawn from D-algorithm.
References
- W. Claeys, S. Dilhaire, and V. Quintard, "Laser probing of thermal behavior of electronic components and its application in quality and reliability testing", Microelectronic Engineering, vol. 24, pp. 441 - 420, 1994. :Elsevier
- J. P. Roth, W. G. Bouricius, and P. R. Schneider, “Programmed Algorithms to Compute Tests to Detect and Distinguish Between Failures in Logic Circuits,” IEEE Trans. on Electronic Computers, vol. EC-16, no. 5, pp. 567–580, Oct. 1967.
Questions and Answers
- Using path sensitization and Routh’s algebra generate test pattern for the s-a- fault in the circuit given below: A
B E
s-a-
Answer: To sensitize the fault, 1 is to be applied at the output of the AND gate. Also, there is only one path for fault propagation-- fault location to E. Now, to justify we need to apply a 0 at the second input of the OR gate. This leads to a collision. For justification we need a 0 in the second input of the OR gate and to sensitize the fault B is to be 1, which makes the second input of the OR gate a 1. This is illustrated in the figure below in terms of Routh’s algebra. A =
B = E
s-a-
D
0 D (Conflict)
Now, since there is no other alternative path for fault propagation, this fault is not testable. In fact the answer is true. This fault is not testable. This example actually illustrates another utility of ATPG algorithm—finding redundancy in circuits. If we observer carefuuly, function represented by this circuit is: E=A.B+B. This can be simplified as B(A+1), which is B. So these two gates are redundant. So, if ATPG by path sensitization discovers that a fault is not testable, then there is redundancy in the circuit.
From the table it may be noted that for 0 at the output of the AND gate only one input needs to be specified and the other is X. So we have 2 choices (0X and X0) for the singular cover of a 2-input AND gate for output =0. But for output =1 there is only one choice. Similarly, for the OR gate we have 2 choices (1X and X1) for the singular cover for output =1; for output=0 we have a single choice. In a similar way, singular cover for any gate can be found.
Definition 2: D-frontier The D-frontier comprises gates whose output value is X and at least one of its input
is D or D. This implies that, any gate in D-frontier can be used for fault propagation. This is explained by an example given in Figure 1.
a =X
b =
c =X
d =X
e
s-a-0 i (^) X
D
X
D
f
g (^) h
j
Figure 1. D-frontier-the encircled gates In Figure 1, let us consider a s-a-0 fault at input line b. The only way to sensitize the fault is to make b =1. Automatically, nets e and i are assigned D. All other nets are assumed to have the value X. Now, D-frontier comprises gates which are encircled. It may be noted that in these gates one input is D and the other is X. The basic idea is, X at the inputs can be appropriately selected so that D or D can be propagated to the output of the gates. In other words, faults can be propagated only through gates in the D-frontier. Once the fault
is propagated (i.e., the output of the gate has D or D ), the gate is deleted from the D- frontier list.
Definition 3: Unique D-Drive If there is only one gate in D-frontier, then fault effect has to be propagated through that gate. This situation is called unique D-drive.
Definition 4: J-frontier The J-frontier comprises gates whose output value is known (0 or 1) but its inputs are not yet computed (or not yet implied by its inputs). In other words, output of a gate in the J- frontier is known, but inputs are not yet computed. This implies that, any gate in J- frontier can be used for justification. This is explained by an example given in Figure 2.
a =X
b =
c =X
d =X
e
i
X
s-a-
D
D D
f
g (^) h
j
Figure 2. J-frontier--the encircled gates We consider the same circuit as in Figure 1. Assume that it was decided that fault effect D be propagated via j. So, j =D by forward implication. Also, f =0 for propagating D to g. Now, the encircled gate in Figure 2 is in the J-frontier, because the output is known as 0 and its inputs are X, which can be decided in justification step. The basic idea is, X at the inputs can be appropriately selected so that output is justified. In other words, during justification gates in J-frontier can only be considered. Once the inputs are justified, the gate is deleted from the J-frontier list.
Figure 3 explains the forward implication procedure.
X X (^) a^1 J-frontier={a}
1 (^1) a^1 J-frontier={}
X X
0 a J-frontier={a}
X (^0) a^0 J-frontier={} 0 X (^) a^0 J-frontier={}
X X
1 a J-frontier={a}
1 X a^1 J-frontier={} X 1
1 a J-frontier={} X X
0 a J-frontier={a}
0 (^0) a^0 J-frontier={}
X X
1 1 1
1
Figure 3. Backward implication and J-frontier
In Figure 3, gates at left side represent the case before backward implication and the ones at the right side illustrate the situation after implication The first gate in the sequence (from top) has inputs as X and output as 1; so J-frontier is a. Now by backward implication (i.e., singular cover) both inputs are to be 1. The corresponding gate in right side shows that inputs are decided by backward implication and so gate (a) is removed from J-frontier. In Figure 3, the second gate has output of 0 and so by singular cover we have two options for assigning values to the inputs; the two options are shown in the right side. It may be noted that we could have also kept another option where both the inputs are kept 1. However, this is avoided because if both inputs are fixed then flexibility gets reduced and chances of inconsistency increases. This is explained by an example given in Figure 4. In the figure it may be noted that in Step-2 we have three options (at the input) to obtain D at the output of the AND gate--00,01 and 10. If we choose 10 then we will have inconsistency in Step-4, because to propagate D through the OR gate the input not carrying D is to be 0. To avoid such inconsistencies we maintain as many X as possible to have flexibility for successful forward and backward implications.
X s-a-
X
X
X (^) X s-a-
X
D
X
Step- Step-1 (unique D-drive)
0 s-a-
X
D
X
Step-2 (Backward implication)
0 s-a-
X
D
D
Step-3 (Propagate D through D-Frontier)
D-frontier
0 s-a-
0
D
D
Step-4 (Backward Implication) Figure 4. Propagating D using backward and forward implication
Procedure 5: X-path An X-path is a path of consecutive nets in a circuit all of whose values are X. Let A be a gate in a D-frontier. The faults on the inputs of A can be propagated to a primary output O only if there is an X-path from A to O. In Figure 6 there is only one X-path from a to output— a-c-d.
X D
1
1
X
1
a
b c
X
0
(^0 )
0
d
X
e
f
g
h
Figure 6. Example of an X-path
3. D-Algorithm In this section we will first present the steps involved in D-algorithm. Following that we will elaborate the algorithm using an example. a. D-Algorithm Input: Circuit netlist and one stuck at fault with its location. Output : Primary input values and expected values at the primary outputs
Step-1: Initialize all the signal values of the circuit to X. Step-2: Sensitize the fault location, i.e., if s-a-0 is the fault, apply D in the fault location, else if s-a-1 is the fault, apply D in the fault location.
Step 3: Determine/update gates in D-frontier and J-frontier, due to signal changes from X to 0,1, D or D. If there is no gate in D-frontier and D / D has not reached any primary output, backtrack(). Step-4: If D / D has not reached any primary output, propagate D / D through one of the gates in the D-frontier. Step-5: Use forward and backward implications to determine as many signal values as possible. backtrack() in case of an inconsistency. Step-6: If D / D has reached any primary output and the primary inputs have received values by backward implications, stop; the values of the primary inputs comprise the test pattern. Else, go to Step-3.
The module backtrack(), works as follows. Step-1: Determine the last choice (of alternatives) taken in selection of gates in D- frontier or signal values in forward/backward implications, where another new alternative is available. Take any one of the other alternative. If no choice is left, report non testable fault and return. Step-2: Undo all steps (i.e., propagation of D / D and forward/backward implications), from the current signal values to point where another alternative is attempted. Return.
