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© April 2009 Altera Corporation AN 311: Standard Cell ASIC to FPGA Design Methodology and Guidelines
© April 2009 AN-311-3.
AN 311: Standard Cell ASIC to FPGA Design
Methodology and Guidelines
Introduction
The cost of designing traditional standard cell ASICs is increasing every year. In addition to non-recurring engineering (NRE) and mask costs, development costs are increasing due to design complexity. Issues such as power, signal integrity, clock tree synthesis, and manufacturing defects can add significant risk and time-to-market delays. FPGAs offer a viable and competitive option to traditional standard cell ASIC development by reducing the risk of re-spins, high NRE costs, and time-to-market delays. Programmable logic has progressed from being used as glue logic to today’s FPGAs, where complete system designs can be implemented on a single device. The number of gates and features has increased dramatically to compete with capabilities that have traditionally only been offered through ASIC devices. Figure 1 illustrates the evolution of FPGA applications that have led to higher density devices, intellectual property (IP) integration, and high-speed I/O interconnects technology. All of these elements have allowed FPGAs to play a central role in digital systems implementations. With the availability of multimillion-gate FPGA architectures, and support for various third-party EDA tools, you can use a design flow similar to that of traditional standard cell ASIC devices to create system-on-a-programmable-chip (SOPC) designs in FPGAs. In addition, with the Altera®^ Stratix ®^ series of FPGAs, you have a seamless path to HardCopy ®^ ASICs.
Figure 1. Application of FPGA Devices from 1985 to the Present
Glue Logic
Complex Control
SOPC Design
Equations Schematics
Control Logic
Synthesis Macrofunctions
Second-generation Synthesis IP Megafunctions
Block-based Design
Electronic System Level Design
ESL Design C2H
Increasing PLD Complexity
1985 1990 1995 2003 2006
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AN 311: Standard Cell ASIC to FPGA Design Methodology and Guidelines © April 2009 Altera Corporation
With the device sizes and architectures that are available today, FPGAs can effectively implement systems that were once possible only in traditional standard cell ASICs. Because of their programmable capability, FPGAs reduce the time to bring up a system as well as minimize the financial risk involved with new designs. Some of the newer FPGA devices have resources such as on-chip transceivers for different physical layer (PHY) protocols, providing the capability to interface with external memories and implement large blocks of internal memory. All of these aspects help to reduce device count on a board, in turn bringing down the cost associated with the product. Cyclone ®^ series FPGAs provide a low-cost alternative for applications that currently use low-to-moderate-density traditional standard cell ASICs. A rich feature set makes Cyclone series FPGAs suitable for a broad range of applications including displays, wireless communication, video and image processing, automotive, and military at a cost per device that is comparable to traditional standard cell ASICs.
Stratix series FPGAs provide a good alternative to more complex traditional standard cell ASICs. These are high-performance, high-end FPGAs that have resources such as large internal memory, fast external memory interfaces, on-chip transceivers, and a large number of internal clock networks. Stratix GX series devices and Arria ™^ GX devices have on-chip transceivers that support a number of industry-standard serial interfaces in addition to other logic resources. Stratix series FPGA devices, which includes Stratix, Stratix II, Stratix III and Stratix IV, also provides a cost effective migration option for going to volume production with HardCopy ASIC offerings from Altera. By choosing to go to HardCopy ASICs, you can utilize the programmable feature during the design, verification, and prototyping stages, reduce the time to market, and get the cost, power, and performance benefits in production. You can also reduce the typical problems associated with traditional ASICs, such as low yield and issues with testability and reliability.
f For more details about HardCopy ASICs, and for design guidelines for targeting your designs to HardCopy series devices, refer to the HardCopy device handbooks at www.altera.com.
This document is intended for traditional standard cell ASIC designers considering FPGA or HardCopy ASIC implementation of their designs, either for prototyping or for production. This application note gives some guidelines for efficient FPGA implementation of their designs. It also discusses the salient features of Altera’s Quartus ®^ II software that make it easy for building true system-on-a-programmable-chip (SOPC) solutions. Comparisons between typical FPGA and traditional standard cell ASIC design flow are also made whenever applicable.
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AN 311: Standard Cell ASIC to FPGA Design Methodology and Guidelines © April 2009 Altera Corporation
Design Specification
The design specification stage includes the following activities, which will impact the choice of FPGA device: ■ I/O specification
■ System timing requirements and timing constraints
■ Memory requirements ■ Verification methodology
■ Selection of the FPGA family and device, including the speed grade
Figure 2. A Comparison of Traditional Standard Cell ASIC and FPGA Design Flows
Design Specification
Design Development/ Physical and Power Planning
Functional Simulation
Synthesis/Physical (Area, Power, and Timing)
Test Synthesis (Scan Insertion, BIST Synthesis)
Placement and Physical Optimization
Clock Tree Synthesis
Routing
Signal Integrity
Sign-off
Timing and Power Analysis
Formal Verification and Timing Analysis
Formal Verification and Post-Layout Timing Analysis
Skew and Timing Analysis
DRC/ERC, Manual Layout Fixes, Hold Time Fixes
IR drops, X-talk
Functional Simulation
Synthesis (Area, Power, and Timing)
ASIC Design Flow
FPGA Design Flow
RTL (Verilog HDL IP Instantiator)
Design Specifiation
Project Planning, I/O Assignments and Analysis, Preliminary Power Estimation
Tasks Tasks
RTL (Verilog HDL IP Instantiator)
Create a Floor Plan
Power Analysis
Static TimingAnalysis Place and Route
In-System Verification
In-System Verification
Formal Verification
Quartus II In-System Debugging Tools
Board-Level Signal Integrity Sign-off
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© April 2009 Altera Corporation AN 311: Standard Cell ASIC to FPGA Design Methodology and Guidelines
I/O Specification
Altera devices support a wide variety of I/O standards. I/O resources vary depending on the device and family. When you design a traditional standard cell ASIC, you can instantiate I/O pads for a design by specifying the technology I/O buffers in a Verilog HDL or VHDL file to perform simulation and synthesis. At the foundry, the I/Os specified in the RTL are replaced with the technology I/O pads. In an Altera FPGA design flow, you choose the type, location, and I/O settings for all the pins in your design with the Pin Planner, which is part of the Quartus II software. With the Pin Planner, you can validate your I/O assignments by performing legality checks on your design’s I/O pins and surrounding logic. These checks include proper reference-voltage pin usage, valid pin location assignments, and acceptable mixed I/O standards. As part of I/O planning, especially with high-speed designs, you should take board-level signal integrity and timing into account. When you have an FPGA device with high-speed interfaces on a board, the quality of the signal at the far end of the board route, as well as the propagation delay in getting there, are vital for proper system operation.
The Quartus II software provides features to take these factors into consideration, making the software “board-aware.” The Quartus II software can take into account board routing and external devices to generate advanced timing reports and board simulation modeling files.
The Quartus II software provides the following methods of signal integrity analysis: ■ I/O timing using a default or user-specified capacitive load with no signal integrity analysis (default) ■ The Enable Advanced I/O Timing option utilizing a user-defined board trace model to produce enhanced timing reports from accurate, “board-aware” simulation models
■ Full board routing simulation in third-party tools using IBIS or HSPICE I/O models generated by the Quartus II software
f For additional information about using the Pin Planner, refer to the I/O Management chapter in volume 2 of the Quartus II Handbook.
Some Altera device families have dedicated circuitry associated with I/O cells to support multiple channels of serial transceivers. The on-chip transceiver circuitry provides physical coding sublayer (PCS) and physical media attachment (PMA) implementation for PHY protocols, such as PCI Express (PCIe), Gigabit Ethernet, XAUI, SPI, and SONET. By using an FPGA that has integrated transceivers you may be able to reduce the overall device count on your boards and reduce cost.
Number of I/O Pins
Determine the exact number of I/O pins used in your design. With this information, you can select a specific device and package.
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© April 2009 Altera Corporation AN 311: Standard Cell ASIC to FPGA Design Methodology and Guidelines
For more information about how to address your memory requirements in Altera FPGAs, refer to “Specification of External and Internal Memory” on page 15.
f For more details about the memory organization in a specific device, refer to the appropriate device handbook.
Verification Methodology
Most of the traditional standard cell ASIC projects start with an exhaustive verification plan and design specifications that are completely frozen. A similar strategy of starting a verification plan early in the design cycle is desirable for today’s complex FPGA designs. Decisions such as whether to use formal verification methods should be made early. The Altera design flow supports industry standard simulation and formal verification tools to aid you with verification.
A key difference in verification methodology between standard cell ASIC-based systems and FPGA/HardCopy ASIC-based systems is the ability to utilize in-system, at-speed verification of your hardware and software, enabling true software and hardware co-design and co-verification. This change in the verification methodology of your chip and system designs is a key contributor to saving millions of dollars and months of time in getting your system to market.
FPGA Device Sizing
Estimate the size of your design so that you can arrive at the power and heat dissipation requirements. After the size of the logic is estimated and operating frequencies are specified, the approximate size and speed grade of the device can be selected.
Altera FPGAs also support vertical migration within the same package. In this context, you can migrate between devices whose dedicated pins, configuration pins, and power pins are the same for a given package across device densities. For example, you can migrate a design from an EP1S10B672C6 device to an EP1S20B672C6 device in the 672-pin package.
Number of Low-Skew Signals
Identify the number of clocks required in your design to choose the FPGA for your implementation. There is usually an upper limit to the number of different low-skew signals available in a device. Clock tree insertion is a manual process in the traditional standard cell ASIC flow, whereas in an FPGA flow it is an automatic process. In most cases, the Quartus II software can automatically choose which low-skew resources to assign to which signals. In addition, it can also determine which signals should be routed on low-skew resources. However, you can make these assignments manually.
Altera FPGAs provide a variety of clocking resources in each device. Clocks that are to be used in all regions of the chip can be routed over global clock nets, which are guaranteed to be low skew. The global clock networks span the entire general purpose logic arrays, feeding all architectural structures. Internal logic, PLL outputs, or device inputs might drive these low-skew global clock resources. You can also use these low-skew global resources for other device-wide signals with large fan-outs, such as asynchronous resets or clock enables. The number of device wide low-skew resources
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available is device dependent. Stratix devices provide fast regional clocks in addition to the global low-skew resources. Similarly, Stratix II, Stratix III, and Stratix IV devices provide a hierarchical clocking structure consisting of global clocks (GCLKs), regional clocks (RCLKs), and peripheral clocks (PCLKs). You can use a combination of these low-skew signals to route clocks and other high fan-out signals in your design. In addition to the clock networks described previously, Stratix GX series devices feature separate clock distribution resources that connect directly to the clocking resources of the device logic array. This architecture makes it flexible for reference clock generation, clock domain translation, and support of multi-channel functionality.
1 The Quartus II software turns off unused clock networks to reduce power dissipation in the device. It can also disable unused portions of clock networks for Stratix II, Stratix III, and Stratix IV devices, and can optimize the placement to minimize the portion of the clock network used to further reduce power.
f For more information about regional clocks and fast regional clocks, refer to the Area and Timing Optimization chapter in volume 2 of the Quartus II Handbook.
f For more information about the clocking resources such as GCLK, PCLK, and RCLK within a specific device, refer to the appropriate device handbook.
For more information about clock tree synthesis and clock requirements, refer to “Clock Tree Synthesis” on page 23.
Phase-Locked Loop (PLL) Requirements
Inserting PLL circuitry into a traditional standard cell ASIC device is typically a manual process in which you instantiate special PLL blocks in the design. In the Altera FPGA flow, you can create configurable PLLs with the MegaWizard ®^ Plug-In Manager, available in the Quartus II software. You can control PLL parameters such as phase shift, clock switchover, and PLL bandwidth using the MegaWizard Plug-In Manager. In the PLLs available in Altera devices, each output of the PLL can be programmed independently, creating customizable clock frequencies that are independent of other input or output clocks. Inherent jitter filtration and fine-grained control of the configurable range help you generate the high-performance precision clocks required in your system. The number of PLLs available in FPGA technology is usually limited, whereas PLL quantities are virtually unlimited in traditional standard cell ASIC technology.
f For more information about the number and type of PLLs supported in a specific device, refer to the appropriate chapter on Clock Networks and PLLs in the Altera device handbooks.
Clock Frequencies
The frequency at which your design is expected to operate is an important factor in choosing the appropriate Altera FPGA for your design. The maximum frequency of operation is affected by several factors, such as logic utilization, routing congestion, and the speed grade of the chosen device.
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AN 311: Standard Cell ASIC to FPGA Design Methodology and Guidelines © April 2009 Altera Corporation
Methodology Selection
Altera’s FPGA design methodology supports both top-down and bottom-up design methodology. FPGA design flows support modular design approaches for bottom-up methodology and hierarchical design partitioning for top-down design methodology, similar to the process used for traditional standard cell ASIC devices. Altera’s design software also supports newer standards such as SystemVerilog that are becoming a part of traditional standard cell ASIC design methodology. For team-based designs that are typical of ASIC-size designs, the Quartus II software supports incremental compilation methodology. For designs using HardCopy ASICs to achieve higher performance than the companion FPGA, it is recommended that you use the HardCopy first flow.
Incremental Compilation
In an incremental compilation flow, you can split a large design into smaller partitions. Team members can work on partitions independently, which can simplify the design process and reduce compilation time. The Quartus II incremental compilation feature preserves the results and performance for unchanged logic in your design as you make changes elsewhere, allowing you to perform more design iterations per day and achieve timing closure more efficiently.
If you want to take advantage of the compilation time savings and performance preservation of Quartus II incremental compilation, plan for an incremental compilation flow from the beginning of your design cycle. Good partition and floorplan design helps lower-level design blocks meet top-level design requirements, reducing the time spent integrating and verifying the timing of the top-level design.
f For more information about design planning and different design approaches, refer to the Design Planning with the Quartus II Software and the Quartus II Incremental Compilation for Hierarchical and Team Based Design chapters in volume 1 of the Quartus II Handbook.
f For further information about using different approaches in design methodology when using third-party synthesis tools, refer to the corresponding chapter in the Synthesis section of the Quartus II Handbook , volume 1.
RTL Coding
RTL coding style becomes important when you target your design to an FPGA because the resources in a device are finite. This application note provides some coding guidelines to improve design performance by taking advantage of the FPGA architecture.
This section provides the following guidelines for the RTL coding of your design when you target an Altera FPGA:
■ Synchronous design practices versus asynchronous designs ■ Synchronous versus asynchronous resets
■ Gated clocks versus clock enables ■ Divided clocks
■ Using data pipelining
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© April 2009 Altera Corporation AN 311: Standard Cell ASIC to FPGA Design Methodology and Guidelines
■ Using encoding schemes ■ Using look-ahead techniques
■ Using logic duplication ■ Using internal buses
f Only some of the RTL coding guidelines are discussed here. For more details about coding guidelines, refer to the Design Recommendations for Altera Devices and the Quartus II Design Assistant chapter and the Recommended HDL Coding Styles chapter in volume 1 of the Quartus II Handbook.
Synchronous Design Practices Versus Asynchronous Designs
Use synchronous design practices to avoid glitches and race conditions inherent in asynchronous design. Conforming to a synchronous design style also makes it easier to perform timing analysis and achieve timing closure.
f For a detailed discussion about synchronous design practices, refer to the Design Recommendations for Altera Devices and the Quartus II Design Assistant chapter in the Synchronous FPGA Design Practices section in volume 1 of the Quartus II Handbook.
Another problem caused by asynchronous signals is that the sampling clock at the receiving end might be too slow compared to the initiating clock. The slow clock at the destination might cause a transition on a signal to be completely missed. Implement a good handshake protocol between asynchronous blocks to ensure proper operation. The following typical design styles contribute to asynchronous designs:
■ Gated clocks ■ Latch inferences
■ Multiple clocks ■ Derived clocks
Synchronous Versus Asynchronous Resets
An asynchronous reset is defined as a way of clearing the contents of a register, independent of the associated clock. Standard cell ASIC libraries consist of registers with and without a built-in reset/clear pin. A register with a built-in reset/clear pin is generally bigger than a register without one.
Sometimes, traditional standard cell ASIC designers use registers without asynchronous reset pins to obtain extra speed and reduce area in a design by using an external gate on the data path of the register for a reset. When the reset is routed through the data pin, the clock must be running when the reset is asserted. Additionally, a synchronous reset signal is treated as any other data signal, so no extra care is required during the routing and timing optimization phase.
In traditional standard cell ASIC designs, internally generated asynchronous resets from a state machine can cause problems in scan testing. A typical problem results from the shifting of test vectors through the flipflops of the state machine, which triggers unintended resets. This is not an issue for FPGAs, which do not have to be scan tested.
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© April 2009 Altera Corporation AN 311: Standard Cell ASIC to FPGA Design Methodology and Guidelines
If reducing the power is the primary reason for using clock gating in your design, you can use dedicated resources available in Altera devices to perform clock gating. Altera FPGAs from the Cyclone III, Cyclone II, Stratix IV, Stratix III, and Stratix II families have dedicated clock control blocks to perform clock gating. You can use these blocks to shut down selected clock networks. Altera recommends that you use the dedicated circuitry when available rather than using a multiplexing logic structure.
1 Stratix IV and Stratix III devices use Altera’s innovative Programmable Power Technology, which lets you select higher performance or lower power on a logic cell basis and reduce the overall power.
f For more details about power management with Stratix III devices, refer to the Stratix III Power Management Design Guide. For more details about power management for Stratix IV devices, refer to AN 514: Power Optimization in Stratix IV FPGAs.
f If you must use clock gating, follow the recommended clock gating method described in the “ Gated Clocks” section in the Design Recommendations for Altera Devices and the Quartus II Design Assistant chapter in volume 1 of the Quartus II Handbook.
Divided Clocks
Many designs require clocks generated by division of a master clock. If you have to create a divided clock, Altera recommends that you use the dedicated PLL circuitry for clock division. If you use clock division logic, make sure you use synchronous counters or state machines to perform clock division. Using ripple clock division can make timing analysis difficult.
f For more details on internally generated clocks, refer to the Design Recommendations for Altera Devices and the Quartus II Design Assistant chapter in volume 1 of the Quartus II Handbook.
Using Data Pipelining
Because FPGAs have many registers, you can use the registers for a pipelined architecture to improve the device performance without incurring any area penalty.
1 When you pipeline your design, make sure you equalize data and control path latency, and modify the testbenches to capture the outputs at the right time.
Using Encoding Schemes
Almost all of today’s designs contain a number of state machines. While designing traditional standard cell ASICs it is common to use some sort of binary encoded state machine to reduce area. On the other hand, FPGAs are register rich, and using a one-hot encoded state machine to reduce the combinational logic required between different states. Because of this, one-hot encoding generally produces better performance results for your state machines in your designs.
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AN 311: Standard Cell ASIC to FPGA Design Methodology and Guidelines © April 2009 Altera Corporation
Using Look-Ahead Techniques
Look-ahead techniques force a portion of the large combinational logic function into the previous clock cycle, and force the remaining logic function to be performed in the next clock cycle. This technique, also known as register balancing, balances the levels of logic between registers, resulting in much faster execution. Thus, by splitting the combinational logic over two clock cycles, your logic can run faster without additional latency.
f The Quartus II software can perform register retiming without any changes in the RTL if the corresponding physical synthesis option is set. For more details about setting this option, refer to the “Gate Level Register Retiming” section in the Power Optimization chapter in volume 2 of the Quartus II Handbook.
Using Logic Duplication
You can improve FPGA performance by minimizing the routing delays. High fan-out is one of the sources of routing delays. You can reduce the number of high fan-out registers by logic duplication. The Quartus II software supports logic duplication as part of the netlist optimization. You can choose to do logic duplication in your RTL as well. Some synthesis tools might see the logic replication in the RTL code as redundant, and might optimize the replicated logic. Synthesis attributes might be required to keep the intended replicated logic.
f For further information about the available Physical Synthesis Optimization options, refer to the Netlist Optimization and Physical Synthesis chapter in volume 2 of the Quartus II Handbook.
f For more details about register duplication and register preservation attributes for synthesis tools, Refer to the Quartus II Integrated Synthesis chapter in volume 1 of the Quartus II Handbook.
Using Internal Buses
Internal buses in traditional standard cell ASIC devices allow various internal modules and external devices to communicate. It is not good design practice to have internal tristate buses. Implement tristate functions only at the I/O level.
If your code contains internal tristate inference, the Quartus II software implements it using multiplexers. However, if your design contains multiple partitions, and you use incremental compilation, the Quartus II software might not be able to infer the correct multiplexing logic due to the lack of visibility. Therefore, it is a good practice not to use internal tristates. Altera FPGAs support tristate buses through the I/O interface to communicate with various on-board devices.
f For more details about coding guidelines, refer to the Design Recommendations for Altera Devices and the Quartus II Design Assistant and the Recommended HDL Coding Styles chapters of the Quartus II Handbook , volume 1.
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f For more information about synchronous memories, refer to AN 210 : Converting Memory from Asynchronous to Synchronous for Stratix & Stratix GX Designs.
External Memory Interfaces
For many of today’s high-memory bandwidth applications, the memory must reside outside the standard cell ASIC or FPGA to provide the required buffer size. The Altera IP MegaStore has pre-verified memory controllers that make it easy for you to design a system with external memory. Altera’s complete memory interface design solutions address today’s high-speed memory interface challenges such as memory controller, I/O design, and board level signal integrity issues. Altera’s solutions include advanced FPGA architectures, customizable MegaCore ®^ functions, Quartus II design software, reference designs, demonstration boards, and simulation models. Altera supports interfaces to SDR SDRAM, DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM and reduced latency DRAM (RLDRAM) with clock frequencies of up to 400 MHz, achieving a throughput up to 1600 Mbps.
f For more details about different external memory interfaces available with different Altera FPGA families, refer to the documentation and reference designs at Altera’s External Memory Solutions Center.
Synthesis
Synthesis is the process of converting a design representation from RTL code to a gate-level netlist. The Quartus II software has an integrated synthesis engine. Altera also supports the use of third-party synthesis tools such as Synplify Pro and Precision RTL from Mentor Graphics. Figure 4 shows a typical synthesis flow. Compared to traditional standard cell ASIC tools, FPGA synthesis tools are much easier to use in terms of complexity and scripting. These tools support all of the popular standard cell ASIC synthesis techniques, including the following techniques: ■ Top-down or bottom-up approach
■ Modular design flow ■ Scripting
f For more information about design methodologies with different synthesis tools supported in the Altera design flow, refer to the Synthesis section in volume 1 of the Quartus II Handbook.
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© April 2009 Altera Corporation AN 311: Standard Cell ASIC to FPGA Design Methodology and Guidelines
Third-Party EDA Tool Support for Synthesis
In addition to the Quartus II integrated synthesis engine, you can use the following third-party tools to perform synthesis:
■ Synplify Pro and Synplify from Synopsys’ Synplicity Business Group ■ LeonardoSpectrum and Precision Synthesis from Mentor Graphics
■ Design Compiler from Synopsys
f For more details about using third party synthesis tools, refer to the corresponding chapter in the Synthesis section in volume 1 of the Quartus II Handbook.
Figure 4. Typical Synthesis Design Flow
Gate-level Simulation
Post Place- and-Route Simulation
Configure device
Yes
No
Timing requirements met?
Constraints
Forward-annotated timing constraints
Technology- specific netlist
Post place-and-route simulation files
Post-synthesis simulation files
Configuration files ( .sof / .pof )
Quartus II software
Synthesis
Functional Simulation
VHDL Verilog HDL
Place- and-Route
Synplify Pro, Precision Synthesis, Tech.lib or Quartus II
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© April 2009 Altera Corporation AN 311: Standard Cell ASIC to FPGA Design Methodology and Guidelines
DSP Builder
Altera FPGAs have digital signal processing (DSP) blocks, such as dedicated multiplier blocks, and support embedded processors. These features make Altera FPGAs very suitable for use in such applications. In addition, the Altera design flow provides tools that make designing for DSP much easier.
The Altera DSP portfolio consists of proven, high-performance, standard algorithms and functions created to meet today’s rapidly evolving technologies. Every function in Altera’s MegaCore function library has been rigorously tested and meets the exacting requirements of various industry standards. Altera provides an extensive portfolio of drop-in DSP functions. The DSP portfolio includes everything you require to build SOPC solutions. You can choose blocks of IP from a comprehensive range of standard DSP functions to create a complete SOPC solution. You can instantiate each function multiple times in different designs. The IP library includes functions such as filters, transforms, encoders, error detection and correction circuits, and video and image processors.
Altera’s DSP Builder integrates the Quartus II software with high-level algorithmic development tools such as MATLAB and Simulink software. The DSP Builder software helps you create the hardware representation of a DSP design in an algorithm-friendly development environment. Figure 6 shows a simple design, built from concept-to-implementation, using the DSP Builder. Several ready-to-use mathematical functions are available within both the MATLAB and Simulink tools, along with simulation models, which can be used to create a schematic. DSP Builder can generate a RTL description of the design, along with the test bench. Figure 6. DSP Builder Design Flow
Drag and drop
Generate VHDL, Synthesize, and place-and-route
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AN 311: Standard Cell ASIC to FPGA Design Methodology and Guidelines © April 2009 Altera Corporation
The MegaWizard Plug-In Manager
The MegaWizard Plug-In Manager helps you create or modify design files that contain custom megafunction variations, which can then be instantiated in a design file.
C2H Compiler
With the evolution of HDLs, digital systems are being described at increasingly higher levels of abstraction. Newer standards such as SystemVerilog and SystemC are offshoots of this development. Many traditional standard cell ASIC designers now model their designs in a high-level language such as C for verification of the architectural design and model implementation. Several design tools are now available to help you to take your concept from a high-level language to hardware implementation, thereby reducing the design cycle.
To support the high-level design flow, Altera provides the C2H Compiler as part of the Nios II Embedded Design Suite. This tool creates custom hardware for functionality that would otherwise require processor usage. Creating a dedicated logic in hardware can improve the execution performance. You can decide on the blocks required for the acceleration requirement you may decide to generate. The C2H Compiler takes code written in ANSI-style C and maps it into resources in an Altera FPGA.
f For more details on using the Nios II C2H Compiler, refer to the Nios II C2H Compiler User Guide.
IP Availability and Flow
IP blocks that are pre-verified reduce the design time, solve many time-to-market issues, and simplify verification. Altera has an extensive offering of specialty IP cores which you can incorporate directly into your design. These include embedded processors, specialty communications interfaces, and memory controllers. These pre-verified cores help you reduce the time to market. These IP cores are designed to take advantage of Altera’s device architecture, thus ensuring optimal fit results. You can also find many reference designs using these IP cores on Altera’s website.
f For a list of IP cores available for Altera devices, go to www.altera.com/literature/lit-ip.jsp.
Altera delivers IP cores as a single MegaCore®^ IP library package that is built into the Quartus II software download file and installation process. The MegaWizard Plug-In Manager allows you to quickly and easily view documentation, specify parameters, set up third-party tools, and generate the files necessary for integrating the parameterized Altera IP core into a design
f For more information about the IP design flow, refer to the Designing With Altera Intellectual Property page on the Altera website.
