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Address Instruction-Advance Computer Architecture-Lecture Slides, Slides of Advanced Computer Architecture

Gujarat University Advanced Computer Architecture

This course focuses on quantitative principle of computer design, instruction set architectures, datapath and control, memory hierarchy design, main memory, cache, hard drives, multiprocessor architectures, storage and I/O systems, computer clusters. This lecture includes: Address, Bytes, Operand, Double, Encoding, Arithmatic, Shift, Branch, Jump, Register, Call

Typology: Slides

2011/2012

Uploaded on 08/06/2012

amrusha 🇮🇳

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1-address instruction

Code size = 1+3= 4 bytes

# of bytes accessed from memory

4 bytes for instruction fetch +

3 bytes for source operand fetch +

0 bytes for storing destination operand

Total = 7 bytes

1 byte 3 bytes

op code source 2

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Download Address Instruction-Advance Computer Architecture-Lecture Slides and more Slides Advanced Computer Architecture in PDF only on Docsity!

1-address instruction

Code size = 1+3= 4 bytes

# of bytes accessed from memory

4 bytes for instruction fetch +

3 bytes for source operand fetch +

0 bytes for storing destination operand

Total = 7 bytes

1 byte 3 bytes

op code source 2

0-address instruction

Code size = 1 bytes

# of bytes accessed from memory

1 bytes for instruction fetch +

6 bytes for source operand fetch +

3 bytes for storing destination operand

Total = 10 bytes

1 byte

op code

RISC and MIPS ISA

RISC and MIPS is a fixed length, 64-bit

LOAD/STORE Architecture

Contains 32 GPR each of 32-bit

Supports:

3-address, reg-reg arithmetic instruction
displacement instructions with address offset

12-16 bits

immediate data 8-bit and 16-bit and
register indirect
data size 8-, 16-, 32- and 64-bit integer
64-bit IEEE 754 floating point

RISC and MIPS ISA …Cont’d

Supports … cont’d

Instructions:

Data Transfer: load, store,

Simple Arithmetic: add, subtract, and shift
Compare: equal, not-equal, less
Branch: PC-relative, jump and

call/return

Designed for pipelining efficiency

MIPS Instruction Word Format

Op

Rs Rt Rd Func

Register-Register (R-Type)

Sht

Op-code = 000000

Rs and Rt : source operand registers

Rd : Result carrying register

Sht: Number of bit-shift – (left/right)

Func: ALU function to encode the data path operation

Execution: Rd <- Rs func Rt

Example Encoding MIPS

R-Type Arithmetic / Logical Instructions

Arithmetic Instructions

Instruction Name Meaning

DADD R1, R2, R3 Add word (signed) Reg[R1]<-Reg[ R2]+Reg[R3]

DADDU R1, R2, R3 Add unsigned Reg[R1]<-Reg[ R2]+Reg[R3]

Shift Instruction

DSLL R1, R2, # 30 Shift Left Logical Reg[R1]<-Reg[ R2]<< 30

R2 R3 R1 DADD/U

xxx

DSLL

R2 R1 xxx xxxxx

MIPS Operations

Immediate Arithmetic / Logical Instructions

Instruction Name Meaning

DADDIU R1, R2, # 30 Add unsigned Imm Reg[R1]<-Reg[ R2]+Reg[R3]

Load/Store Instructions

Instruction Name Meaning

LW R1, 30 (R2) Load word Reg[R1]<-Mem [30+Reg[ R2]

SW R1, 30(R2) Store word Mem [30+Reg[R2]<- Reg[R1]

DADDIU

R2 R

LW/SW

R2 R

MIPS Instruction Word Format

Op

Rs

Rt

immediate

Branch /Jump Register

Conditional Branch Instructions:

(i) used after the compare or test BEQZ:

Rs is the register and Rt is unused;

Condition test the register for Zero or non-zero

(ii) Condition with the Branch; BNE

Rs and Rt are compared

iii) Jump Register; Jump and Link Register

Rt=0, Rs = Destination and immediate = 0

MIPS Instruction Word Format

Op

target

Jump / Call

Jump: uses 26-bit offset; shifted 2-bit then replace

the lower 28 bits of PC [ of the instruction following

the jump

Jump and Link (Procedure Call) place the return

address; the address of the next instruction in R

used for Return from procedure

MIPS Operations

Jump/Call

Instruction Name Meaning

J name Jump PC

36..

<- name

JAL R4 Jump and Link Reg [R31] <- PC+4; PC

36..

<- name;

J/JAL

R4 xxxx

(PC+4)-

<= name< (PC+4)-

Summary

MIPS Instruction word format

RISC and MIPS is a fixed length, 64-bit LOAD/STORE

Architecture

It supports: Size of Operand

Character (8-bit)

Half word (16-bit)

Single precision FP or Word (32-bit)

Double precision FP or double word (64-bit)

Instruction word formats

R-type, I-type and J-type

Address Instruction-Advance Computer Architecture-Lecture Slides, Slides of Advanced Computer Architecture

Related documents

Partial preview of the text

Download Address Instruction-Advance Computer Architecture-Lecture Slides and more Slides Advanced Computer Architecture in PDF only on Docsity!

1-address instruction

Code size = 1+3= 4 bytes

# of bytes accessed from memory

4 bytes for instruction fetch +

3 bytes for source operand fetch +

0 bytes for storing destination operand

Total = 7 bytes

1 byte 3 bytes

op code source 2

0-address instruction

Code size = 1 bytes

# of bytes accessed from memory

1 bytes for instruction fetch +

6 bytes for source operand fetch +

3 bytes for storing destination operand

Total = 10 bytes

1 byte

op code

RISC and MIPS ISA

RISC and MIPS ISA …Cont’d

MIPS Instruction Word Format

Op

Rs Rt Rd Func

Register-Register (R-Type)

Sht

Op-code = 000000

Rs and Rt : source operand registers

Rd : Result carrying register

Sht: Number of bit-shift – (left/right)

Func: ALU function to encode the data path operation

Execution: Rd <- Rs func Rt

R-Type Arithmetic / Logical Instructions

Instruction Name Meaning

R2 R3 R1 DADD/U

xxx

DSLL

R2 R1 xxx xxxxx

MIPS Operations

Instruction Name Meaning

DADDIU R1, R2, # 30 Add unsigned Imm Reg[R1]<-Reg[ R2]+Reg[R3]

Instruction Name Meaning

LW R1, 30 (R2) Load word Reg[R1]<-Mem [30+Reg[ R2]

SW R1, 30(R2) Store word Mem [30+Reg[R2]<- Reg[R1]

DADDIU

R2 R

LW/SW

R2 R

MIPS Instruction Word Format

Op

Rs

Rt

immediate

Branch /Jump Register

MIPS Instruction Word Format

Op

target

Jump / Call

MIPS Operations

J/JAL

R4 xxxx

(PC+4)-

Summary

Architecture

Allah Hafiz

and

Asalm-u-Alacum