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This course focuses on quantitative principle of computer design, instruction set architectures, datapath and control, memory hierarchy design, main memory, cache, hard drives, multiprocessor architectures, storage and I/O systems, computer clusters. This lecture includes: Address, Bytes, Operand, Double, Encoding, Arithmatic, Shift, Branch, Jump, Register, Call
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RISC and MIPS is a fixed length, 64-bit
LOAD/STORE Architecture
Contains 32 GPR each of 32-bit
Supports:
12-16 bits
Supports … cont’d
Instructions:
register-register move
call/return
Designed for pipelining efficiency
Example Encoding MIPS
Arithmetic Instructions
DADD R1, R2, R3 Add word (signed) Reg[R1]<-Reg[ R2]+Reg[R3]
DADDU R1, R2, R3 Add unsigned Reg[R1]<-Reg[ R2]+Reg[R3]
Shift Instruction
DSLL R1, R2, # 30 Shift Left Logical Reg[R1]<-Reg[ R2]<< 30
Immediate Arithmetic / Logical Instructions
Load/Store Instructions
Conditional Branch Instructions:
(i) used after the compare or test BEQZ:
Rs is the register and Rt is unused;
Condition test the register for Zero or non-zero
(ii) Condition with the Branch; BNE
Rs and Rt are compared
iii) Jump Register; Jump and Link Register
Rt=0, Rs = Destination and immediate = 0
Jump: uses 26-bit offset; shifted 2-bit then replace
the lower 28 bits of PC [ of the instruction following
the jump
Jump and Link (Procedure Call) place the return
address; the address of the next instruction in R
used for Return from procedure
Jump/Call
Instruction Name Meaning
J name Jump PC
36..
<- name
JAL R4 Jump and Link Reg [R31] <- PC+4; PC
36..
<- name;
27
<= name< (PC+4)-
27
MIPS Instruction word format
Character (8-bit)
Half word (16-bit)
Single precision FP or Word (32-bit)
Double precision FP or double word (64-bit)
R-type, I-type and J-type