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A transition table based on these equations is shown in Table 7-4(a). Reading
the logic diagram, we can write two output equations:
The resulting output values are shown in the last column of (a). Assigning state
names A–H, we obtain the state/output table shown in (b).
A state diagram for the example machine is shown in Figure 7-44. Since
our example is a Moore machine, the output values are written with each state.
Each arc is labeled with a transition expression ; a transition is taken for input
combinations for which the transition expression is 1. Transitions labeled “1”
are always taken.
T a b l e 7 - 4 Transition/output and state/output tables for the state machine in Figure 7-43.
(a) X Y (b) X Y Q2 Q1 Q0 00 01 10 11 Z1 Z2 S 00 01 10 11 Z1 Z 000 000 100 001 001 10 A^ A^ E^ B^ B^10 001 001 001 011 011 10 B^ B^ B^ D^ D^10 010 010 110 000 000 10 C^ C^ G^ A^ A^10 011 011 011 010 010 00 D^ D^ D^ C^ C^00 100 101 101 101 101 11 E^ F^ F^ F^ F^11 101 001 001 001 001 10 F^ B^ B^ B^ B^10 110 111 111 111 111 11 G^ H^ H^ H^ H^11 111 011 011 011 011 11 H^ D^ D^ D^ D^11 Q2∗ Q1∗ Q0∗ S∗
Z1 = Q2 + Q1′ + Q0′
Z2 = Q2 ⋅ Q1 + Q2 ⋅ Q0′
A X Z1 Z2 = 10
B Z1 Z2 = 10
C X Z1 Z2 = 10
D Z1 Z2 = 00
E 1 Z1 Z2 = 11
F Z1 Z2 = 10
G 1 Z1 Z2 = 11
H Z1 Z2 = 11 1
1
X X
X′ •^ Y′
X′ •^ Y
X′ •^ Y
X′ •^ Y′
X′
X′
Fi g ur e 7 - 4 4 State diagram corresponding to Table 7-4.
transition expression
Substituting into the characteristic equation for J-K^ flip-flops, we obtain the
transition equations:
A transition table based on these equations is shown in Table 7-5(a). Reading the
logic diagram, we can write the output equation:
The resulting output values are shown in each column of (a) along with the next
state. Assigning state names A–D, we obtain the state/output table shown in (b).
A corresponding state diagram that uses transition expressions is shown in
Figure 7-46.
T a b l e 7 - 5 Transition/output and state/output tables for the state machine in Figure 7-45.
(a) X Y (b) X Y
Q1 Q0 00 01 10 11 S 00 01 10 11 00 00, 0 10, 1 01, 0 10, 1 A^ A, 0 C, 1 B, 0 C, 1 01 01, 0 11, 0 10, 0 11, 0 B^ B, 0 D, 0 C, 0 D, 0 10 10, 0 00, 0 11, 0 00, 0 C^ C, 0 A, 0 D, 0 A, 0 11 11, 0 10, 0 00, 1 10, 1 D^ D, 0 C, 0 A, 1 C, 1 Q1∗ Q0∗, Z S∗, Z
Q0∗ = J0 ⋅ Q0′ + K0′ ⋅ Q
= X ⋅ Y′ ⋅ Q0′ + (X ⋅ Y′ +^ Y ⋅ Q1)′ ⋅ Q
= X ⋅ Y′ ⋅ Q0′ +^ X′ ⋅ Y′ ⋅ Q0 +^ X′ ⋅ Q1′⋅ Q0 +^ Y ⋅ Q1′⋅ Q
Q1∗ = J1 ⋅ Q1′ + K1′ ⋅ Q
= (X ⋅ Q0 +^ Y)^ ⋅ Q1′ + (Y ⋅ Q0′ +^ X ⋅ Y′ ⋅ Q0)′⋅ Q
= X ⋅ Q1′⋅ Q0 +^ Y ⋅ Q1′ +^ X′ ⋅ Y′ ⋅ Q1 +^ Y′ ⋅ Q1 ⋅ Q0′ +^ X′ ⋅ Q1 ⋅ Q0 +^ Y ⋅ Q1 ⋅ Q
Z = X ⋅ Q1 ⋅ Q0 + Y ⋅ Q1′ ⋅ Q0′
X′ •^ Y X •^ Y
A B
C D
X •^ Y′
X •^ Y′
X •^ Y′
X •^ Y′
Y
X′ •^ Y′
X′ •^ Y′
X′ •^ Y′
X′ •^ Y′
Y Y (Z = 1) (Z = 1)
(Z = 1)
Fi g ur e 7 - 4 6 Z = 0 unless otherwise indicated State diagram corresponding to the state machine of Table 7-5.
Section 7.4 Clocked Synchronous State-Machine Design 581
The 1s-counting machine can use two state variables to code its four states,
with no unused states. In this case, there are only 4! possible assignments of
coded states to named states. Still, we’ll try only one of them. We’ll assign coded
states to the named states in Karnaugh-map order (00, 01, 11, 10) for two
reasons: in this state table, it minimizes the number of state variables that
change for most transitions, potentially simplifying the excitation equations;
and it simplifies the mechanical transfer of information to excitation maps.
A transition/excitation table based on our chosen state assignment is
shown in Table 7-13. Since we’re using D flip-flops, the transition and excitation
tables are the same. Corresponding Karnaugh maps for D1 and D2 are shown in
Figure 7-57. Since there are no unused states, all of the information we need is in
the excitation table; no choice is required between minimal-risk and minimal-
cost approaches. The excitation equations can be read from the maps, and the
output equation can be read directly from the transition/excitation table:
A logic diagram using D^ flip-flops and AND-OR^ or NAND-NAND^ excitation
logic can be drawn from these equations.
X Y T a b l e 7 - 1 3 Transition/excitation and output table for 1s-counting machine.
Q1 Q2 00 01 11 10 Z 00 00 01 11 01 1 01 01 11 10 11 0 11 11 10 00 10 0 10 10 00 01 00 0 Q1∗ Q2∗ or D1 D
D1 = Q2 ⋅ X′ ⋅ Y + Q1′ ⋅ X ⋅ Y + Q1 ⋅ X′ ⋅ Y′ + Q2 ⋅ X ⋅ Y′
D2 = Q1′ ⋅ X′ ⋅ Y + Q1′ ⋅ X ⋅ Y′ + Q2 ⋅ X′ ⋅ Y′ + Q2′ ⋅ X ⋅ Y
Z = Q1′ ⋅ Q2′
00 01 10 00 01 11 10
00 01 11 10
X Y Q1 Q 00 01 11 10
X
Y
Q
Q
D1 (^) X Y Q1 Q
X
Q
Q
D
1
1
1 0 1 1 0
1 0 0
0 0 0 1 1 0
0 1 1 1 1 1 0 1 1 0 0 0 0 0 1 0
11
Y Q1 •^ X′ •^ Y′
Q1′ •^ X •^ Y
Q2 •^ X •^ Y′ Q2 •^ X′ •^ Y′
Q2 •^ X′ •^ Y
Q2′ •^ X •^ Y
Q1′ •^ X′ •^ Y Q1′ •^ X •^ Y′ (^) Fi g ur e 7 - 5 7 Excitation maps for D1 and D2 inputs in 1s-counting machine.
Section 7.4 Clocked Synchronous State-Machine Design 583
The combination lock’s eight states can be coded with three state variables,
leaving no unused states. There are 8! state assignments to choose from. To keep
things simple, we’ll use the simplest, and assign the states in binary counting
order, yielding the transition/excitation table in Table 7-15. Corresponding
Karnaugh maps for D1, D2, and D3 are shown in Figure 7-58. The excitation
equations can be read from the maps:
X T a b le 7 - 1 5 Transition/excitation table for combination- lock machine.
Q1 Q2 Q3 0 1 000 001, 01 000, 00 001 001, 00 010, 01 010 001, 00 011, 01 011 100, 01 000, 00 100 001, 00 101, 01 101 001, 00 110, 01 110 100, 00 111, 01 111 001, 11 000, 00 Q1∗ Q2∗ Q3∗, UNLK HINT
D1 = Q1 ⋅ Q2′ ⋅ X + Q1′ ⋅ Q2 ⋅ Q3 ⋅ X′ + Q1 ⋅ Q2 ⋅ Q3′
D2 = Q2′ ⋅ Q3 ⋅ X + Q2 ⋅ Q3′ ⋅ X
D3 = Q1 ⋅ Q2′ ⋅ Q3′ + Q1 ⋅ Q3 ⋅ X′ + Q2′ ⋅ X′ + Q3′ ⋅ Q1′ ⋅ X′ + Q2 ⋅ Q3′ ⋅ X
Q2′ •^ X′
00 01 10 00 01 11 10
00 01 11 10
X Q1 X Q1 X Q Q2 Q 00 01 11 10
X
Q
Q
Q
Q2 Q
X
Q
Q
Q
Q2 Q
X
Q
Q
Q
D1 D
0
1
1 0 0 0 0
1 0 1
0 0 0 0 0 1
0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1
11
Q1′ •^ Q2 •^ Q3 •^ X′ Q1 •^ Q2 •^ Q3′ Q2 •^ Q3′ •^ X Q2 •^ Q3′ •^ X
Q1 •^ Q2′ •^ X Q2′ •^ Q3 •^ X Q1 •^ Q3 •^ X′
01 10 00 01 11 10
D
1 1 1 0 1 1 0 0 0 1 0 0 1 0 1 1
11
Q1′ •^ Q3′ •^ X′
Q1 •^ Q2′ •^ Q3′
00
Fi g ur e 7 - 5 8 Excitation maps for D1 , D2 , and D3 in combination-lock machine.
If there are many transitions leaving each state, these steps, especially the first
one, are very difficult to perform. However, typical state machines, even ones
with lots of states and inputs, don’t have many transitions leaving each state,
since most designers can’t dream up such complex machines in the first place.
This is where the tradeoff between state-table and state-diagram design occurs.
In state-table design, the foregoing steps are not required, because the structure
of a state table guarantees mutual exclusion and all inclusion. But if there are a
lot of inputs, the state table has lots of columns.
Verifying that a state diagram is unambiguous may be difficult in principle,
but it’s not too bad in practice for small state diagrams. In Figure 7-63, most of
the states have a single arc with a transition expression of 1, so verification is
trivial. Real work is needed only to verify the IDLE state, which has four transi-
tions leaving it. This can be done on a sheet of scratch paper by listing the eight
combinations of the three inputs and checking off the combinations covered by
each transition expression. Each combination should have exactly one check. As
another example, consider the state diagrams in Figures 7-44 and 7-46 on pages
560 and 562; both can be verified mentally.
LR
R3 R
R
IDLE
L
L
LEFT •^ HAZ′ •^ RIGHT′ 1 1
RIGHT •^ HAZ′ •^ LEFT′
1
1 1
HAZ + LEFT •^ RIGHT
L
(LEFT + RIGHT + HAZ)′
1 1
F i gu re 7 - 6 3 Corrected state diagram for T-bird tail lights.
Section 7.5 Designing State Machines Using State Diagrams 589
Returning to the T-bird tail-lights machine, we can now synthesize a circuit
from the state diagram if we wish. However, if we want to change the machine’s
behavior, now is the time to do it, before we do all the work of synthesizing a
circuit. In particular, notice that once a left- or right-turn cycle has begun, the
state diagram in Figure 7-63 allows the cycle to run to completion, even if HAZ
is asserted. While this may have a certain aesthetic appeal, it would be safer for
the car’s occupants to have the machine go into hazard mode as soon as possible.
The state diagram is modified to provide this behavior in Figure 7-64.
Now we’re finally ready to synthesize a circuit for the T-bird machine. The
state diagram has eight states, so we’ll need a minimum of three flip-flops to
code the states. Obviously, many state assignments are possible (8! to be exact);
we’ll use the one in Table 7-16 for the following reasons:
1. An initial (idle) state of 000 is compatible with most flip-flops and regis-
ters, which are easily initialized to the 0 state.
2. Two state variables, Q1 and Q0, are used to “count” in Gray-code sequence
for the left-turn cycle (IDLE→L1→L2→L3→IDLE). This minimizes the
LR
R3 R
R
IDLE
L
L
LEFT •^ HAZ′ •^ RIGHT′ 1 1
RIGHT •^ HAZ′ •^ LEFT′
1
HAZ′ HAZ′ HAZ
HAZ + LEFT •^ RIGHT
L
(LEFT + RIGHT + HAZ)′
HAZ′ HAZ′ HAZ
HAZ
HAZ
Fi g ur e 7 - 6 4 Enhanced state diagram for T-bird tail lights.
The only way to avoid this erroneous behavior in general is to ensure that
changes in P arrive at the inputs of all the excitation circuits before any changes
in state variables do. Thus, the inevitable difference in input arrival times, called
timing skew , must be less than the propagation delay of the excitation circuits
and feedback loops. This timing requirement can generally be satisfied only by
careful design at the electrical circuit level.
In the example circuit, it would appear that the hazard is easily masked,
even by non-electrical engineers, since the designer need only ensure that a
straight wire has shorter propagation delay than an AND-OR structure—easy in
most technologies.
Still, many feedback sequential circuits, such as the TTL edge-triggered D
flip-flop in Figure 7-19, have essential hazards in which the input skew paths
include inverters. In such cases, the input inverters must be guaranteed to be
faster than the excitation logic; that’s not so trivial in either board-level or IC
design. For example, if the excitation circuit in Figure 7-101 were physically
built using AND-OR-INVERT gates, the delay from input changes to Y1_L could
be very short indeed, as short as the delay through a single inverter.
Essential hazards can be found in most but not all fundamental-mode
circuits. There’s an easy rule for detecting them; in fact, this is the definition of
“essential hazard” in some texts:.
- A fundamental-mode flow table contains an essential hazard for a stable
total state S and an input variable X if, starting in state S, the stable total
state reached after three successive transitions in X is different from the
stable total state reached after one transition in X.
P R Y1 Y
Y1∗ Y2∗
00 01 11 10 Z
F ig u re 7 - 1 0 2 Transition table for the pulse-catching circuit, exhibiting an essential hazard.
timing skew
THESE HAZARDS
ARE, WELL,
ESSENTIAL!
Essential hazards are called “essential” because they are inherent in the flow table for a particular sequential function and will appear in any circuit realization of that function. They can be masked only by controlling the delays in the circuit. Compare with static hazards in combinational logic, where we could eliminate hazards by adding consensus terms to a logic expression.
