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It's an informative pdf about 8086 microprocessor
Typology: Study notes
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M. Krishna Kumar
MM/M1/LU3/V1/
It is a 16 bit μp.
-^
8086 has a 20 bit address bus can access upto 2
20
memory
locations ( 1 MB).
-^
It can support upto 64K I/O ports.
-^
It provides 14, 16-bit registers.
-^
It has multiplexed address and data bus AD
15
and A
16
19
M. Krishna Kumar
MM/M1/LU3/V1/
It requires single phase clock with 33% duty cycle toprovide internal timing.
-^
8086 is designed to operate in two modes, Minimum andMaximum.
-^
It can prefetches upto 6 instruction bytes from memory andqueues them in order to speed up instruction execution.
-^
It requires +5V power supply.
-^
A 40 pin dual in line package.
M. Krishna Kumar
MM/M1/LU3/V1/
4
AH^
AL
BH^
BL
CH^
CL
DH^
DL SPBPSI DI
ESCSSSDSIP
1
∑
ADDRESS BUS( 20 )BITS DATA BUS( 16 )BITS
BUS CONTROLLOGIC
8 0 8 6 BUS
2
3
4
6 5
INSTRUCTION QUEUE
8 BIT Q BUS
ALU DATA BUS16 BITS EUCONTROLSYSTEM
TEMPORARY REGISTERS
ALU FLAGS
GENERALREGISTERS
EXECUTION UNIT ( EU )
BUS INTERFACE UNIT
( BIU)
Fig:
M. Krishna Kumar
MM/M1/LU3/V1/
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
40 39 38 37 36 35 34 33 32 31 30 29 28 272625 24 23 22 21
GNDAD NMIINTRCLKGND
14 AD
13 AD
12 AD
11 AD
10 AD
9 AD
8 AD
7 AD
6 AD
5 AD
4 AD
3 AD
2 AD
1 AD
0
V RESET CCAD^15 A16 /^
S^3 A^17
/ S 4 ____ A^19 MN/MX___RD _______LOCK
/S 6
___(WR)
QS______TESTREADY
1
____S^2
___S^1
_____(DEN)
(ALE)
A^18
/ S 5 _____BHE / S
7
RQ / GT
( HOLD) 0
___^
RQ / GT
( HLDA) 1
(M / IO )
(DT / R) ___ S^0
QS
0
________(INTA)
M. Krishna Kumar
MM/M1/LU3/V1/
8086 has two blocks BIU and EU.
-^
The BIU performs all bus operations such as instructionfetching, reading and writing operands for memory andcalculating the addresses of the memory operands.
-^
The instruction bytes are transferred to the instructionqueue.
-^
EU executes instructions from the instruction system bytequeue.
M. Krishna Kumar
MM/M1/LU3/V1/
Both units operate asynchronously to give the 8086 anoverlapping instruction fetch and execution mechanismwhich is called as Pipelining. This results in efficient useof the system bus and system performance.
-^
BIU contains Instruction queue, Segment registers,Instruction pointer, Address adder.
-^
M. Krishna Kumar
MM/M1/LU3/V1/
This queue permits prefetch of up to six bytes ofinstruction code. When ever the queue of the BIU is notfull, it has room for at least two more bytes and at the sametime the EU is not requesting it to read or write operandsfrom memory, the BIU is free to look ahead in the programby prefetching the next sequential instruction.
-^
These prefetching instructions are held in its FIFO queue.With its 16 bit data bus, the BIU fetches two instructionbytes in a single memory cycle.
-^
M. Krishna Kumar
MM/M1/LU3/V1/
The EU accesses the queue from the output end. It readsone instruction byte after the other from the output of thequeue. If the queue is full and the EU is not requestingaccess to operand in memory.
-^
These intervals of no bus activity, which may occurbetween bus cycles are known as
Idle state
M. Krishna Kumar
MM/M1/LU3/V1/
: The Execution unit is responsible
for decoding and executing all instructions.
-^
The EU extracts instructions from the top of the queue inthe BIU, decodes them, generates operands if necessary,passes them to the BIU and requests it to perform the reador write bys cycles to memory or I/O and perform theoperation specified by the instruction on the operands.
-^
M. Krishna Kumar
MM/M1/LU3/V1/
If the queue is empty, the EU waits for the next instructionbyte to be fetched and shifted to top of the queue.
-^
When the EU executes a branch or jump instruction, ittransfers control to a location corresponding to another setof sequential instructions.
-^
M. Krishna Kumar
MM/M1/LU3/V1/
Minimum Mode Signals
( MN/ MX
= Vcc
)
Name
Function
Type
HOLD
Hold Request
Input
HLDA
Hold Acknowledge
Output
WR
Write Control
Output
,
3- state
M/IO
Memory or IO Control
Output
, 3-State
DT/R
Data Transmit
/
Receiver
Output
, 3- State
DEN
Date Enable
Output
,
3-State
ALE
Address Latch Enable
Output
INTA
Interrupt Acknowledge
Output
(^
/^
=^
)
HLDA
Write Control
,
M/IO
,
DT/R
, 3- State
DEN
,
3-State
ALE INTA
M. Krishna Kumar
MM/M1/LU3/V1/
Maximum mode signals ( MN / MX = GND )Name
Function
Type
RQ / GT1, 0
Request / Grant BusAccess Control
Bidirectional
LOCK
Bus Priority Lock Control
Output,3- StateOutput,3- StateOutput
S^2
0
Bus Cycle Status
QS1, QS
Instruction Queue Status
M. Krishna Kumar
MM/M1/LU3/V1/
The 16 data bus lines D
0
through D
15
are actually
multiplexed with address lines A
0
through A
15
respectively. By multiplexed we mean that the bus work asan address bus during first machine cycle and as a data busduring next machine cycles. D
15
is the MSB and D
0
When acting as a data bus, they carry read/write data formemory, input/output data for I/O devices, and interrupttype codes from an interrupt controller.
M. Krishna Kumar
MM/M1/LU3/V1/ Vcc
GND
A-A^0
,A 15
/S 16
/S 19 6
Address / data bus D^0
15
ALEBHE / S
7
M / IODT / RRD WR DENREADY
CLK clock
MN / MX
Vcc
Mode select
INTRINTA TEST NMI RESET HOLDHLDA
8086 MPU
Interruptinterface DMAinterface
MemoryI/O controls
