Docsity
Docsity

Prepare for your exams
Prepare for your exams

Study with the several resources on Docsity


Earn points to download
Earn points to download

Earn points by helping other students or get them with a premium plan


Guidelines and tips
Guidelines and tips

80386 Microprocessor Architecture, Lecture notes of Microprocessors

80386 Microprocessor Architecture

Typology: Lecture notes

2018/2019
On special offer
30 Points
Discount

Limited-time offer


Uploaded on 04/03/2019

aditya-ghongade
aditya-ghongade 🇮🇳

5

(1)

2 documents

1 / 101

Toggle sidebar

This page cannot be seen from the preview

Don't miss anything!

bg1
80386 MICROPROCESSOR
ARCHITECTURE
Prof. P. C. Patil
Department of Computer Engg
Sandip Institute of Engineering & Management
Nashik
pc.patil@siem.org.in
MICROPROCESSOR
UOP S.E.COMP (SEM-II)
1
pf3
pf4
pf5
pf8
pf9
pfa
pfd
pfe
pff
pf12
pf13
pf14
pf15
pf16
pf17
pf18
pf19
pf1a
pf1b
pf1c
pf1d
pf1e
pf1f
pf20
pf21
pf22
pf23
pf24
pf25
pf26
pf27
pf28
pf29
pf2a
pf2b
pf2c
pf2d
pf2e
pf2f
pf30
pf31
pf32
pf33
pf34
pf35
pf36
pf37
pf38
pf39
pf3a
pf3b
pf3c
pf3d
pf3e
pf3f
pf40
pf41
pf42
pf43
pf44
pf45
pf46
pf47
pf48
pf49
pf4a
pf4b
pf4c
pf4d
pf4e
pf4f
pf50
pf51
pf52
pf53
pf54
pf55
pf56
pf57
pf58
pf59
pf5a
pf5b
pf5c
pf5d
pf5e
pf5f
pf60
pf61
pf62
pf63
pf64
Discount

On special offer

Partial preview of the text

Download 80386 Microprocessor Architecture and more Lecture notes Microprocessors in PDF only on Docsity!

80386 MICROPROCESSOR

ARCHITECTURE

Prof. P. C. Patil Department of Computer Engg Sandip Institute of Engineering & Management Nashik pc.patil@siem.org.in

MICROPROCESSOR

UOP S.E.COMP (SEM-II)

Introduction

Block Diagram

 These signals are separated in Six major groups :

  1. Bus / Memory Interface Unit
  2. Code Prefetch Unit
  3. Instruction Decode Unit
  4. Execution Unit
  5. Segmentation Unit
  6. Paging Unit

Pin Discription

Bus Status Signals :

 The bus status signals decide the type of bus cycle to be

performed. These signals are :

_1. Address status

  1. Write/Read
  2. Memory/IO
  3. Data/Control
  4. LOCK_

Pin Discription

Register Set

General Purpose Register

Segment Registers

  1. CS (Code Segment) : holds the base address of the currently active code segment.
  2. DS (Data Segment) : is used to hold the address of currently active data segment.
  3. ES (Extra Segment) FS, & GS : are used as general data segment registers.  These registers hold the base addresses of three different memory segments.  These segments are referred as to Extra Segments.
  4. SS (Stack Segment) : The base address of the currently active. stack segment is contained in the SS register.

Segment Register

lndex, Pointers & Base Registers