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74x138 3-to-8 Decoder
The 74x138 is a commercially available MSI 3-to-8 decoder whose gate- level circuit diagram and symbol are shown in Figure 7; its truth table is given in Table. Like the 74x139, the 74x has active-low outputs, and it has three enable inputs (G1, /G2A, /G2B), all of which must be asserted for the selected output to be asserted.
The logic function of the 74X138 is straightforward—an output is asserted if and only if the decoder is enabled and the output is selected.
Thus, we can easily write logic equations for an internal output signal such as Y5 in terms of the internal input signals:
However, because of the inversion bubbles, we have the following relations between internal and external signals:
Therefore, if we’re interested, we can write the following equation for the external output signal Y5_L in terms of external input signals:
On the surface, this equation doesn’t resemble what you might expect for a decoder, since it is a logical sum rather than a product. However, if you practice bubble-to-bubble logic design, you don’t have to worry about this; you just give the output signal an active-low name and remember that it’s active low when you connect it to other inputs.
The 74x148 is a commercially available, MSI 8-input priority encoder it has an enable input, EI_L, that must be asserted for any of its outputs to be asserted. The complete truth table is given in Table 5-22. Instead of an IDLE output, the ’148 has a GS_L output that is asserted when the device is enabled and one or more of the request inputs is asserted. The manufacturer calls this “Group Select” but it’s easier to remember as “Got Something” The EO_L signal is an enable output designed to be connected to the EI_L input of another ’ that handles lower-priority requests. /EO is asserted if EI_L is asserted but no request input is asserted; thus, a lower-priority ’148 may be enabled.
Figure 6-49 shows how four 74x148s can be connected in this way to accept 32 request inputs and produce a 5-bit output, RA4-RAO, indicating the highest-priority requestor. Since the A2-AO outputs of at most one' 148 will be enabled at any time, the outputs of the individual' 148s can be ORed to produce RA2-RAO. Likewise, the individual GS_L outputs can be combined in a 4-to-2 encoder to produce RA4 and RA3. The RGS output is asserted if any GS output is asserted.
The 74x148 is a commercially available, MSI 8-input priority encoder it has an enable input, EI_L, that must be asserted for any of its outputs to be asserted. The complete truth table is given in Table 5-22. Instead of an IDLE output, the ’148 has a GS_L output that is asserted when the device is enabled and one or more of the request inputs is asserted. The manufacturer calls this “Group Select” but it’s easier to remember as “Got Something” The EO_L signal is an enable output designed to be connected to the EI_L input of another ’ that handles lower-priority requests. /EO is asserted if EI_L is asserted but no request input is asserted; thus, a lower-priority ’148 may be enabled.
Figure 6-49 shows how four 74x148s can be connected in this way to accept 32 request inputs and produce a 5-bit output, RA4-RAO, indicating the highest-priority requestor. Since the A2-AO outputs of at most one' 148 will be enabled at any time, the outputs of the individual' 148s can be ORed to produce RA2-RAO. Likewise, the individual GS_L outputs can be combined in a 4-to-2 encoder to produce RA4 and RA3. The RGS output is asserted if any GS output is asserted.
When “010”=>y 2 <=Din;
When “011”=>y 3 <=Din;
When “100”=>y 4 <=Din;
When “101”=>y 5 <=Din;
When “110”=>y 6 <=Din;
When “111”=>y 7 <=Din;
When “others”=>y<=’0’;
End case;
Following figure shows the logic diagram and symbol for a 74x245 octal three-state transceiver. The DIR input determines the direction 74x245 of transfer, from A to B (DIR=
- or from B to A (DIR= 0). The three-state buffer for the selected direction is enabled only if G_L is asserted.
The below given example is for 4-bit gray code to binary code and for program refer my class note (OR) write a dataflow style VHDL program for the simplified expressions.
