Docsity
Docsity

Prepare for your exams
Prepare for your exams

Study with the several resources on Docsity


Earn points to download
Earn points to download

Earn points by helping other students or get them with a premium plan


Guidelines and tips
Guidelines and tips

7 Questions on Operating Systems - Exam 1 | CSC 4310, Exams of Computer Science

Material Type: Exam; Class: PARALLEL & DIST COMPUTING; Subject: COMPUTER SCIENCE; University: Georgia State University; Term: Unknown 1989;

Typology: Exams

Pre 2010

Uploaded on 08/31/2009

koofers-user-g2n
koofers-user-g2n 🇺🇸

10 documents

1 / 8

Toggle sidebar

This page cannot be seen from the preview

Don't miss anything!

bg1
CSC 43210/6320 Operating System Exam 1
Name: _________________________
Question Number Score
1
2
3
4
5
6
7
Total:
pf3
pf4
pf5
pf8

Partial preview of the text

Download 7 Questions on Operating Systems - Exam 1 | CSC 4310 and more Exams Computer Science in PDF only on Docsity!

CSC 43210/6320 Operating System Exam 1

Name: _________________________

Question Number Score

Total:

Explain the following terminology: (3pts each)

1. Process

2. I/O-bound process

3. Symmetric multiprocessing

4. spinlock

5. Adaptive mutexes

6. Race Condition

7. Monitor

1. Process: a program in execution

2. I/O-bound process: spends more time doing I/O than computations,

many short CPU bursts

3. Symmetric multiprocessing: each processor is self-scheduling. Each

processor may have their own ready queue.

4. spinlock: the process “spins” while waiting for the lock and doing

nothing useful

5. Adaptive mutexes: If a lock is held by a thread that is currently

running on another CPU, the thread spins while waiting for the lock,

because the thread holding the lock is likely to finish soon. If the

thread holding the lock is not currently in run state, the thread blocks,

going to sleep until it is awaken by the release of the lock

6. Race Condition: several processes access and manipulate the same

data concurrently and the outcome of the execution depends on the

particular order in which the access takes place.

7. Monitor: A high-level abstraction that provides a convenient and

effective mechanism for process synchronization. Only one process

may be active within the monitor at a time

According to the bounded buffer code in shared memory system we

discussed in the class, draw the ring structure with size 4 and indicate the

location of “in” and “out” for each time space. (If the buffer is full or

empty, indicates how many jobs are waiting) (10pts, 2 pts for each)

Producer View while (true) { /* produce an item and put in next Produced/ while (count == BUFFER_SIZE) ; // do nothing buffer [in] = nextProduced; in = (in + 1) % BUFFER_SIZE; count++; } Consumer View while (true) { while (count == 0) ; // do nothing nextConsumed= buffer[out]; out = (out + 1) % BUFFER_SIZE; count--; / consume the item in next Consumed }

Time Action in:1 out:

1 Producer produces 3 jobs 4 1

2 Consumer consumes 1 job 4 2

3 Producer produces 2 jobs 2 2

4 Consumer consumes 3 jobs 2 1

5 Consumer consumes 3 jobs 2 2

In the MPI programming we discussed in the class (also showed below), P0 (the id for CPU is 0) is the server who owned the full array and distributed array information to other CPUs. For other CPUs, they wait for receiving those data.

__________________________________________________________

if (id==0) { for(i=0; i<array_size; i++) array[i]=i; /* initialize array/ for(i=1; i<p; i++) MPI_Send(&array[iarray_size/p], /* Start from/ array_size/p, / Message size/ MPI_INT, / Data type/ i, / Send to which process/ MPI_COMM_WORLD); for(i=0; i<array_size/p; i++) local_array[i]=array[i]; } else MPI_Recv(&local_array[0],array_size/p,MPI_INT,0,0,MPI_COMM_WORLD,&stat); Assume we have 8 CPUs, the network of those CPUs looks like below: Instead of using P0 as the only master; we use both P0 and P6 as the masters. (P0 is the master for P through P3; P6 is the master for P4 through P7) Both of them generate the initial array only for their responsibility portion. Write a code similar to I showed you above that matches the criteria. Every line above should have a corresponding line(s) in your answer. (15 pts) If (id==0){ for (i=0; i<array_size/2;i++) array[i]=i; for (i=1; i<4; i++) MPI_Send(&array[iarray_size/p], array_size/p, MPI_INT, i, MPI_COMM_WORLD); for (i=0; i<array_size/p; i++) local_array[i]=array[i]; } If (id==6){ for (i= array_size/2; i<array_size;i++) array[i]=i; for (i=4; i<7; i++) if (i != 6) MPI_Send(&array[iarray_size/p], array_size/p, MPI_INT, i, MPI_COMM_WORLD); for (i=0; i<array_size/p; i++) local_array[i]=array[2 (array_size/p) + i]; } if (id==1 or id==2 or id==3) MPI_Recv(&local_array[0],array_size/p,MPI_INT,0,0,MPI_COMM_WORLD,&stat); if (id==4 or id==5 or id==7) MPI_Recv(&local_array[0],array_size/p,MPI_INT,6,0,MPI_COMM_WORLD,&stat);

6.1 A solution to the critical-section problem must satisfy which three requirements? (6pts) Mutual Exclusion Progress Bounded Waiting 6.2 We consider a system consisting of two processes, P0 and P1, each accessing two semaphores, S and Q, set to the value 1. P0 P Wait(S) Wait(Q) Wait(Q) Wait(S) … … … … … … Signal(S) Signal(Q) Signal(Q) Signal(S) What kind of unwanted situation will happen? (3%) Explain your answer? (3%) Deadlock Occurs 6.3 We consider a system consisting of two processes, P0 and P1, each accessing two semaphores, S and Q, set to the value 1. P0 P Wait(S) Wait(S) Wait(Q) Wait(Q) … … … … … … Signal(S) Signal(Q) Signal(S) Signal(S) What kind of unwanted situation(s) will happen? (4%) Explain your answer? (4%) Starvation (Deadlock) Violate Mutual exclusion

If we applied timestamp-Based Protocols on the following schedule: T0 T1 T Timestamp: 2 4 6. Operation: R(A) R(A) R(A) W(A) W(A) 7.1 If the execution sequence happens like: T0’s R(A) T0’s W(A) T2’s R(A) T2’s W(A) T1’s R(A) Is there any transaction need “Roll Back”? If yes, which one and why? If no, just say no. (3 pts) Yes, T 7.2 If the execution sequence happens like: T0’s R(A) T0’s W(A) T2’s R(A) T1’s R(A) T2’s W(A) Is there any Transaction need “Roll Back”? If yes, which one and why? If no, just say no. (3 pts) No 7.3 If the execution sequence happens like: T0’s R(A) T1’s R(A) T0’s W(A) T2’s R(A) T2’s W(A) Is there any Transaction need “Roll Back”? If yes, which one and why? If no, just say no. (3 pts) Yes, T