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6 Problems for Final Exam - Digital Logic Design | ENEE 244, Exams of Electrical and Electronics Engineering

Material Type: Exam; Class: Digital Logic Design; Subject: Electrical & Computer Engineering; University: University of Maryland; Term: Spring 1998;

Typology: Exams

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ENEE244-Digital Logic Design
SPRING SEMESTER 1998
FINAL/May 18, 1998
CLOSED BOOKS AND NOTES
Exam Period: 90 Minutes
Instructions:
1. Use the space provided below each problem. Should you need more space, ask the proctor.
2. Write your name and student Id. No. on the cover sheet.
3. Promptly turn in your exam to the proctor when the exam is declared to be over.
Problem 1:(30)
Problem 2:(25)
Problem 3:(25)
Problem 4:(30)
Problem 5:(25)
Problem 6:(25)
Name:
Student ID:
pf3
pf4
pf5

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Download 6 Problems for Final Exam - Digital Logic Design | ENEE 244 and more Exams Electrical and Electronics Engineering in PDF only on Docsity!

ENEE244-Digital Logic Design SPRING SEMESTER 1998 FINAL/May 18, 1998 CLOSED BOOKS AND NOTES Exam Period: 90 Minutes

Instructions:

  1. Use the space provided below each problem. Should you need more space, ask the proctor.
  2. Write your name and student Id. No. on the cover sheet.
  3. Promptly turn in your exam to the proctor when the exam is declared to be over.

Problem 1:(30) Problem 2:(25) Problem 3:(25) Problem 4:(30) Problem 5:(25) Problem 6:(25)

Name: Student ID:

Problem 1: (30 points.) Given the function below

f (A, B, C, D) = A′B′C′^ + AC′^ + A′B′CD′^ + ACD′

(a) List the minterms of f (^) ∑ (0, 1 , 2 , 8 , 9 , 10 , 12 , 13 , 14)

(b) List the maxterms of f (^) ∏ (3, 4 , 5 , 6 , 7 , 11 , 15)

(c) List the prime implicants of f and specify those which are essential.

AC′, B′D′, AD′, B′C′

(d) Complement f ′^ = A′B + CD to obtain a NAND circuit with four NAND gates.

Decoder

Initial state Problem 3:(25 points.) A 4-bit message, d 1 , d 2 , d 3 , d 4 , is to be passed through combinational circuit which is designed to invert all four bits in the message when it operates correctly. However, the circuit occasionally fails to invert all four bits. Assuming that it fails to invert at most one of the bits, modify the combinational circuit so that it can identify and correct the bit which is not inverted. Problem 4:(30 points.) A sequential circuit has one input, x and one output, z. The output z is to be 1 if the number of 1’s the circuit has received is not divisible by 2 and the number of 0’s it has received is divisible by 3. (a) Give a Mealy state diagram for this machine and indicate the initial state.

  • d1 d2 d3 d - c - c - c - 3X - c - d - c - d - d - d - c - correct d - correct d - correct d - correct d - 1 / 0 1 / - 0 / 0 1 / - 0 / - 0 / 1 0 / - 0 / - 0 / - 1 / - 0 / - 0 / - 1 / - 1 / - 1 / - 1 / - 1 / - 1 / - 1 /
    • 0 /
    • 0 /
      • 0 /
  • 0 / - 1 /

0 1 2 3 4 5 6 7 8 9

1 0 1 1

State Code Next State^ Code 3 4 5 6 7 8 9

1 0 1 1 3 4 5

0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1

0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 0 0 1 1 0 1 0 0 0 1 0 1

x=0 (^) x= Next State Code 1 2 1 4 5 4 7 8 7

1 0 1 1 1 0

0 0 0 1 0 0 1 0 0 0 0 1 0 1 0 0 0 1 0 1 0 1 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 1 0 1 0 1 1 1 0 1 0

y 0y 1 y 2y 3

Y0 = Σ (5 , 6 , 7 , 8 , 2 3 , 2 5 , 2 6 , 2 7 ) Y1 = Σ (1,2,3,4,10,11,20,21,22,24) Y2 = Σ (0 , 3 , 4 , 7 , 8 , 9 , 1 7 , 2 2 , 2 4 , 2 5 , 2 6 , 2 7 ) Y3 = Σ (0 , 2 , 4 , 6 , 8 , 9 , 1 1 , 1 6 , 1 8 , 2 0 , 2 2 , 2 4 , 2 6 , )

D 16X1MPX

y 0y 1 y 2y 3

D 16X1MPX

y 0y 1y 2 y 3

D 16X1MPX

y 0y 1y 2 y 3

D 16X1MPX

y 0y 1 y 2y 3 (^00) (^00) (^0) x ' x ' 1 x 'x xx

Q0 (^) Q1 (^) Q Q

(^0) x ' x ' 1 (^1) x x 0 x 0 x 'x '

x 'x (^0) x ' x '0 ' xx ' (^11) xx

(^10) (^10) (^10) (^10) (^1) x ' xx '

Problem 4 (b):

J K

J K

J K

J K

f 1 f 2

f 1 f 2

f 1 f 2

f 1 f 2

Q1 Q2 (^) Q3 (^) Q

(^0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 ) 4X1MPX 4X MPX 4X1MPX 4X1MPX

Q2 Q4 Q1 Q1' (^) Q3 Q1 Q2 Q2' (^) Q4 Q2 Q3 Q3' (^) Q1 Q3 Q4 Q4'

Problem 6: (25 points.) (a) A 4-bit register with two function select inputs f 1 and f 2 is to be designed. The register is to function as follows:

f1 f2 function

0 0 Rotate left 0 1 Rotate right 1 0 No change 1 1 Complement

Give an implementation of this register using J-K flip flops and other logic elements as needed.