CPSC 5155 Introduction to Computer Architecture
Homework Set 4 Due Monday, March 20, 2006
NOTE: SHOW ALL OF YOUR WORK. YOU MUST DEMONSTRATE THAT YOU
UNDERSTAND THE PROCESS OF OBTAINING AN ANSWER. WHILE THESE CAN
BE DONE ON MANY CALCULATORS, YOU MUST DO THESE BY HAND.
BE PREPARED TO DISCUSS THESE PROBLEMS IN CLASS.
1. A 16Mb memory chip (224 bits) is organized as a 2D array of bits.
a) How many address lines are used for the chip?
b) If the chip is organized to be as “square” as possible, how many bits are
in the row address and how many bits in the column address?
c) What size SRAM buffer should be attached to this chip for faster row access?
2. A secondary memory with a 60–nanosecond access time is fronted by a cache memory
with a 4–nanosecond access time. What is the effective access time, if
a) The cache hit ratio is 0.95?
b) The cache hit ratio is 0.99?
c) The cache hit ratio is 0.999?
3. Suppose that a 16M by 32 main memory in which each 32–bit word is addressable.
Note that this implies that the bytes in the memory are not individually addressable.
a) How many addressable words are found in the memory?
b) How many bits must be in the MAR in order for the memory to be addressed?
c) How many bits must be in the MBR?
4. Suppose that a 16M by 32 main memory is built using 1MB by 8 RAM chips and
that memory is 32–bit word addressable.
a) How many RAM chips are necessary?
b) How many address bits are sent to each RAM chip?
c) How many address bits would be used to select the RAM chip?
d) Assuming low–order interleaving, which address bits will select the RAM chip
and which bits are sent to each RAM chip?
5. The following is a memory map for a byte–addressable memory. What is the value
of the 32–bit long integer stored at address X, if
a) The memory is organized in Little–Endian fashion?
b) The memory is organized in Big–Endian fashion?
Give these numbers as decimal values.
Address Contents
X 0x10
X + 1 0x12
X + 2 0x20
X + 3 0x30