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4 Solved Problems on a Tomasulo Algorithm - Homework 3 | CS 538, Assignments of Computer Architecture and Organization

Material Type: Assignment; Professor: Archer; Class: COMP ARCHITECTURE; Subject: Computer Science; University: Portland State University; Term: Spring 2007;

Typology: Assignments

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CS538 Homework 3 Spring, 2007
1. This exercise examines the basic Tomasulo algorithm. Answer the following
questions based upon the tabular descriptions of the algorithm given in
Figure 3.5, without examining the solution in the book.
a. (5 points) For each row of the table, state (1) whether that row
could apply simultaneously to more than one program instruction
(that is, ILP); (2) whether the Tomasulo algorithm allows ILP for
that row; (3) if ILP is not allowed, how that restriction is enforced;
and (4) if ILP is allowed, what if anything could prevent achieving the
maximum ILP present in the program.
b. (5 points) Which one of rs and rt holds the name of the base
address register for a load or store instruction? Explain your answer
in sufficient detail to be a proof.
c. (5 points) In the terminology of the table, write the function(s)
performed by the Address unit in Figure 3.2.
d. (5 points) Write the table entries required to support integer ALU
operation instructions.
e. (5 points) Consider how branch instructions affect the instruction
processing described in the table. Show the modifications to the
table necessary to take the presence of branch instructions in the
program into account.
2. (25 points) Consider the execution of the following code segment:
DIV.D F4, F10, F9
MUL.D F5, F1, F4
ADD.D F1, F2, F3
MUL.D F7, F8, F9
Trace the execution of this code segment on a 5-stage pipeline (fetch,
issue, read-operands, execute, writeback) architecture which uses
Tomasulo's algorithm to dynamically schedule instructions (single issue per
cycle - no speculation). Show the instruction status, the reservation station
status and register results status at cycles 3, 6, 9, 12 and 15. Assume the
following non-pipelined execution units:
- a 2-cycle FP adder
- a 3-cycle FP multiplier
- a 6-cycle FP divider
Assume that two reservation stations are used for each functional unit
(add1, add2, mult1, mult2, div1, div2). You may find the template on the
following page useful for this exercise.
pf3
pf4

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  1. This exercise examines the basic Tomasulo algorithm. Answer the following questions based upon the tabular descriptions of the algorithm given in Figure 3.5, without examining the solution in the book. a. (5 points) For each row of the table, state (1) whether that row could apply simultaneously to more than one program instruction (that is, ILP); (2) whether the Tomasulo algorithm allows ILP for that row; (3) if ILP is not allowed, how that restriction is enforced; and (4) if ILP is allowed, what if anything could prevent achieving the maximum ILP present in the program. b. (5 points) Which one of rs and rt holds the name of the base address register for a load or store instruction? Explain your answer in sufficient detail to be a proof. c. (5 points) In the terminology of the table, write the function(s) performed by the Address unit in Figure 3.2. d. (5 points) Write the table entries required to support integer ALU operation instructions. e. (5 points) Consider how branch instructions affect the instruction processing described in the table. Show the modifications to the table necessary to take the presence of branch instructions in the program into account.
  2. (25 points) Consider the execution of the following code segment: DIV.D F4, F10, F MUL.D F5, F1, F ADD.D F1, F2, F MUL.D F7, F8, F Trace the execution of this code segment on a 5-stage pipeline (fetch, issue, read-operands, execute, writeback) architecture which uses Tomasulo's algorithm to dynamically schedule instructions (single issue per cycle - no speculation). Show the instruction status, the reservation station status and register results status at cycles 3, 6, 9, 12 and 15. Assume the following non-pipelined execution units:
    • a 2-cycle FP adder
    • a 3-cycle FP multiplier
    • a 6-cycle FP divider Assume that two reservation stations are used for each functional unit (add1, add2, mult1, mult2, div1, div2). You may find the template on the following page useful for this exercise.

Time: Clock cycle ## (Assumption: at the end of each clock cycle) Instruction status (indicate with an x) Instructions (^) Issue Execute Write result DIV.D F4, F10, F MUL.D F5, F1, F ADD.D F1, F2, F MUL.D F7, F8, F

Reservation status (fill in appropriate values) Name (^) Busy Op Vj Vk Qj Qk A Add Mult Mult Div

Register Status (fill in with appropriate values) F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F Qi

  1. This exercise explores variations on the theme of the example on page 221 of the text. Each part of this exercise lists changes to make to the set of assumptions given in the example. For each part, produce a new version of the table in Figure 3.25, covering enough iterations to reach a steady- state condition, and compute a value for the sustained instruction completion rate: a. (15 points) Assume that there are two integer functional units. b. (15 points) Assume that three instructions may issue simultaneously, but that the BNE still issues separately.