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Half-hour Examination #1 for CEG 360/560 and EE 451/651 Spring 99 Courses by Dr. Doom - Pr, Exams of Digital Systems Design

The half-hour examination #1 for the ceg 360/560 and ee 451/651 courses taught by dr. Doom during spring 99. The examination covers topics related to flip-flops, sequential circuits, and digital design. Students are allowed to use one page of notes during the closed-book exam. Three problems that require the determination of the number of states, the characteristic equation, and the state diagram for an ab-type flip-flop, as well as the analysis of a clocked synchronous state machine and the calculation of its timing parameters.

Typology: Exams

Pre 2010

Uploaded on 08/16/2009

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CEG 360/560 - EE 451/651 Dr. Doom
Spring 99 15 Apr 99
Half-hour Examination #1 - 30 minutes
Closed Book, Undergraduates may use one page of notes
________________________________________________________________________________________________
NAME ___________________________________ COURSE __________ SCORE _____ / 34
_______________________________________________________________________________________
Problem #1: [14] The questions on this page refer the AB-type flip-flop, described below.
A B Q(t+1)
0 0 Q'(t)
0 1 1
1 0 Q(t)
1 1 0
(a) [2 pts.] How many states does this device have? Is Q a Mealy or Moore output?
(b) [4 pts.] Determine the characteristic equation of the AB-type flip-flop (show your work).
(c) [4 pts.] Draw a state diagram for the AB-type flip-flop.
(d) [4 pts.] Design an implementation of an AB-type flip-flop using a D-type positive-edge triggered flip-
flop and a multiplexer. [Hint: The input logic should implement the characteristic equation for the device].
Use proper documentation practices: label all connections with the appropriate Boolean expressions. Points
will be deducted for needlessly inefficient circuits.
________________________________________________________________________________________________
A Q
Clk
B
pf3
pf4
pf5

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Download Half-hour Examination #1 for CEG 360/560 and EE 451/651 Spring 99 Courses by Dr. Doom - Pr and more Exams Digital Systems Design in PDF only on Docsity!

Spring 99 15 Apr 99

Half-hour Examination #1 - 30 minutes

Closed Book, Undergraduates may use one page of notes


NAME ___________________________________ COURSE __________ SCORE _____ / 34


Problem #1: [14] The questions on this page refer the AB-type flip-flop, described below. A B Q(t+1) 0 0 Q'(t) 0 1 1 1 0 Q(t) 1 1 0 (a) [2 pts.] How many states does this device have? Is Q a Mealy or Moore output? (b) [4 pts.] Determine the characteristic equation of the AB-type flip-flop (show your work). (c) [4 pts.] Draw a state diagram for the AB-type flip-flop. (d) [4 pts.] Design an implementation of an AB-type flip-flop using a D-type positive-edge triggered flip- flop and a multiplexer. [Hint: The input logic should implement the characteristic equation for the device]. Use proper documentation practices: label all connections with the appropriate Boolean expressions. Points will be deducted for needlessly inefficient circuits.

A Q

Clk

B

Spring 99 15 Apr 99

Half-hour Examination #1 - 30 minutes

Closed Book, Undergraduates may use one page of notes


Problem #2: [16] Analyze the clocked synchronous state machine given below. (a) [2 pts.] Input Equations D1 = D0 = (b) [2 pts.] Transition Equations Q1(t+1) = Q0(t+1) = (c) [1 pt.] Output Equation Z = (d) [1 pt.] Circle One Z is Mealy Z is Moore (e) [4 pts.] State/Output Table X Q1(t)Q0(t) 0 1 00 01 10 11 Q1(t+1)Q0(t+1)/Z This design is implemented with LS devices having the following characteristics: 74LS00 propagation delay, input to output (max): 17 ns input to output (min): 3 ns DFFRS propagation delay, clock to output (max): 13 ns clock to output (min): 8 ns DFFRS setup time, data input before clock: 10 ns DFFRS hold time, data input after clock: 7 ns Calculate the timing parameters for the design. (f) [1 pts.] Prop. delay, clock to output (max): (g) [1 pts.] Prop. delay, input to output (min): (h) [1 pts.] Setup time, data input before clock: (i) [1 pts.] Hold time, data input after clock: (j) [2 pts.] Maximum clock rate:

DFFRSPRDCLKREQQ' 7400 / 47400 / 40 XDFFRSPRDCLKREQQ'VCCClk 050 n 100 n VCC 1 Z

Spring 99 15 Apr 99

Half-hour Examination #1 - 30 minutes

Closed Book, Undergraduates may use one page of notes


Signature : ________________________________________________

Spring 99 15 Apr 99

Half-hour Examination #1 - 30 minutes

Closed Book, Undergraduates may use one page of notes


**DO NOT BEGIN UNTIL INSTRUCTED TO DO SO



DO NOT BEGIN UNTIL INSTRUCTED TO DO SO**