



Study with the several resources on Docsity
Earn points by helping other students or get them with a premium plan
Prepare for your exams
Study with the several resources on Docsity
Earn points to download
Earn points by helping other students or get them with a premium plan
Community
Ask the community for help and clear up your study doubts
Discover the best universities in your country according to Docsity users
Free resources
Download our free guides on studying techniques, anxiety management strategies, and thesis advice from Docsity tutors
The half-hour examination #1 for the ceg 360/560 and ee 451/651 courses taught by dr. Doom during spring 99. The examination covers topics related to flip-flops, sequential circuits, and digital design. Students are allowed to use one page of notes during the closed-book exam. Three problems that require the determination of the number of states, the characteristic equation, and the state diagram for an ab-type flip-flop, as well as the analysis of a clocked synchronous state machine and the calculation of its timing parameters.
Typology: Exams
1 / 5
This page cannot be seen from the preview
Don't miss anything!
Spring 99 15 Apr 99
NAME ___________________________________ COURSE __________ SCORE _____ / 34
Problem #1: [14] The questions on this page refer the AB-type flip-flop, described below. A B Q(t+1) 0 0 Q'(t) 0 1 1 1 0 Q(t) 1 1 0 (a) [2 pts.] How many states does this device have? Is Q a Mealy or Moore output? (b) [4 pts.] Determine the characteristic equation of the AB-type flip-flop (show your work). (c) [4 pts.] Draw a state diagram for the AB-type flip-flop. (d) [4 pts.] Design an implementation of an AB-type flip-flop using a D-type positive-edge triggered flip- flop and a multiplexer. [Hint: The input logic should implement the characteristic equation for the device]. Use proper documentation practices: label all connections with the appropriate Boolean expressions. Points will be deducted for needlessly inefficient circuits.
Spring 99 15 Apr 99
Problem #2: [16] Analyze the clocked synchronous state machine given below. (a) [2 pts.] Input Equations D1 = D0 = (b) [2 pts.] Transition Equations Q1(t+1) = Q0(t+1) = (c) [1 pt.] Output Equation Z = (d) [1 pt.] Circle One Z is Mealy Z is Moore (e) [4 pts.] State/Output Table X Q1(t)Q0(t) 0 1 00 01 10 11 Q1(t+1)Q0(t+1)/Z This design is implemented with LS devices having the following characteristics: 74LS00 propagation delay, input to output (max): 17 ns input to output (min): 3 ns DFFRS propagation delay, clock to output (max): 13 ns clock to output (min): 8 ns DFFRS setup time, data input before clock: 10 ns DFFRS hold time, data input after clock: 7 ns Calculate the timing parameters for the design. (f) [1 pts.] Prop. delay, clock to output (max): (g) [1 pts.] Prop. delay, input to output (min): (h) [1 pts.] Setup time, data input before clock: (i) [1 pts.] Hold time, data input after clock: (j) [2 pts.] Maximum clock rate:
Spring 99 15 Apr 99
Signature : ________________________________________________
Spring 99 15 Apr 99
**DO NOT BEGIN UNTIL INSTRUCTED TO DO SO
DO NOT BEGIN UNTIL INSTRUCTED TO DO SO**